公开(公告)号：EP3053198A1

公开(公告)日：2016-08-10

申请号：EP14850973.0

申请日：2014-09-26

Applicant: Vishay General Semiconductor LLC

Inventor： CHEN, Shih-Kuan ,  CHIANG, Wan-Lan ,  LIN, Yih-Yin ,  CHIANG, Ming-Tai ,  PENG, Chih-Ping

IPC: H01L29/866

CPC classification number: H01L29/0611 ,  H01L21/2253 ,  H01L21/2257 ,  H01L21/2652 ,  H01L21/283 ,  H01L29/456 ,  H01L29/66106 ,  H01L29/66113 ,  H01L29/861 ,  H01L29/866

Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.

公开(公告)号：EP3002789A1

公开(公告)日：2016-04-06

申请号：EP15187232.2

申请日：2015-09-28

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： OUERGHI, Issam ,  ERNST, Thomas ,  GRENOUILLET, Laurent

IPC: H01L27/12 ,  H01L27/06

CPC classification number: H01L21/324 ,  H01L21/02675 ,  H01L21/2652 ,  H01L21/76224 ,  H01L23/552 ,  H01L27/1203 ,  H01L27/1248 ,  H01L27/1274 ,  H01L31/0547 ,  H01L31/1864 ,  H01L31/1872 ,  H01L2924/0002 ,  Y02E10/52 ,  H01L2924/00

Abstract: Procédé de réalisation d'éléments semi-conducteurs à base de matériau semi-conducteur cristallin, comprenant des étapes consistant à :
a) prévoir un support (10-11-12-15) comportant des éléments semi-conducteurs à base de matériau semi-conducteur amorphe, le support étant doté en outre d'un ou plusieurs composants (T 1 , T 2 ) et d'une zone de protection réfléchissante configurée de manière à réfléchir un rayonnement lumineux dans une gamme de longueur d'ondes donnée,
b) exposer le ou les éléments (2) à un rayonnement laser (5) émettant dans ladite gamme de longueurs d'ondes donnée de manière à recristalliser lesdits éléments, la zone de protection réfléchissante étant agencée sur le support par rapport aux éléments et aux composants de manière à réfléchir le rayonnement laser et protéger les composants de ce rayonnement (figure 1).

公开(公告)号：EP2713385A1

公开(公告)日：2014-04-02

申请号：EP13182241.3

申请日：2013-08-29

Applicant: Boe Technology Group Co. Ltd.

Inventor： Ma, Zhanjie

IPC: H01L21/265 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L21/265 ,  H01L21/24 ,  H01L21/2652 ,  H01L29/66742 ,  H01L29/66757

Abstract: Disclosed are an active layer ion implantation method and an active layer ion implantation method for thin-film transistor. The active layer ion implantation method comprises: applying a photoresist on the active layer; and implanting ions into the active layer through the photoresist.

Abstract translation: 公开了用于薄膜晶体管的有源层离子注入方法和有源层离子注入方法。 有源层离子注入方法包括：在有源层上施加光致抗蚀剂; 并通过光致抗蚀剂将离子注入有源层。

公开(公告)号：EP2412016A4

公开(公告)日：2014-03-19

申请号：EP10756493

申请日：2010-03-25

Applicant: NAT SEMICONDUCTOR CORP

Inventor： BULUCEA CONSTANTIN ,  FRENCH WILLIAM D ,  ARCHER DONALD M ,  YANG JENG-JIUN ,  BAHL SANDEEP R ,  PARKER D COURTNEY

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

公开(公告)号：EP2412025A4

公开(公告)日：2014-03-12

申请号：EP10756483

申请日：2010-03-25

Applicant: NAT SEMICONDUCTOR CORP

Inventor： YANG JENG-JUIN ,  BULUCEA CONSTANTIN ,  BAHL SANDEEP R

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

公开(公告)号：EP2230686A3

公开(公告)日：2013-07-03

申请号：EP10152536.8

申请日：2010-02-03

Applicant: Fujitsu Semiconductor Limited

Inventor： Shima, Masashi

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device includes, forming an isolation region defining a first region and a second region, injecting a first impurity of a first conductivity type into the first region and the second region, forming a first gate insulating film and a first gate electrode over the first region, forming a second gate insulating film and a second gate electrode over the second region, forming a first mask layer over a first portion of the second region to expose a second portion of the second region and the first region, and injecting a second impurity of the first conductivity type into the semiconductor substrate from a direction diagonal to a surface of the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括：形成限定第一区域和第二区域的隔离区域，将第一导电类型的第一杂质注入到第一区域和第二区域中，形成第一栅极绝缘膜和第一栅极 在所述第一区域之上形成第二栅极绝缘膜和第二栅极电极;在所述第二区域的第一部分之上形成第一掩模层以暴露所述第二区域和所述第一区域的第二部分;以及 从与半导体衬底的表面对角的方向将第一导电类型的第二杂质注入到半导体衬底中。

公开(公告)号：EP2412018A1

公开(公告)日：2012-02-01

申请号：EP10756495.7

申请日：2010-03-25

Applicant: National Semiconductor Corporation

Inventor： BULUCEA, Constantin ,  YANG, Jeng-Jiun ,  FRENCH, William, D. ,  BAHL, Sandeep, R. ,  PARKER, D. Courtney

IPC: H01L21/70 ,  H01L29/02 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: Insulated-gate field-effect transistors (IGFETs), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E). Alternatively or additionally, a more heavily doped pocket portion (250 or 290) of the body material extends along one of the source/drain zones. When present, the pocket portion typically causes the IGFET to be an asymmetric device.

公开(公告)号：EP1399965B1

公开(公告)日：2011-01-12

申请号：EP01996286.9

申请日：2001-12-14

Applicant: Spansion LLC

Inventor： YANG, Jean, Yee-Mei ,  RAMSBEY, Mark, T. ,  LINGUNIS, Emmanuil, Manos ,  WU, Yider ,  KAMAL, Tazrien ,  HE, Yi ,  HSIA, Edward ,  SHIRAIWA, Hidehiko

IPC: H01L21/8247 ,  H01L21/336

CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L27/11568 ,  H01L29/66833

Abstract: One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

公开(公告)号：EP1986240A3

公开(公告)日：2008-11-12

申请号：EP08162077.5

申请日：2003-10-23

Applicant: Fujitsu Limited

Inventor： Anezaki, Toru, Fujitsu Limited

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L21/8247 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8239 ,  H01L27/105

CPC classification number: H01L21/823462 ,  H01L21/2652 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two or more layers and formed on side walls of the gate electrode, the first laminated side wall spacers including a nitride film as a layer other than an outermost layer, the outermost layer being made of an oxide film or an oxynitride film and having a bottom surface contacting the semiconductor substrate, the gate oxide film or a side wall spacer layer other than the nitride film. The semiconductor device may further comprise second laminated side wall spacers having three or more layers and formed on side walls of a laminated gate electrode structure, the second laminated side wall spacers including a nitride film as an intermediate layer not contacting the semiconductor substrate. There is also provided the integration of a memory area and a logic area on the same substrate, the electrodes in both areas exhibiting side wall spacers as described above. A method for manufacturing such a device is also provided.

Abstract translation: 提供一种半导体器件，其具有具有阻挡功能的绝缘膜侧壁间隔物。 该半导体器件包括：形成在半导体衬底上的栅氧化膜和栅电极; 形成在半导体衬底中的源极/漏极区; 以及具有两层或更多层且形成在所述栅电极的侧壁上的第一叠层侧壁间隔物，所述第一叠层侧壁间隔物包括作为最外层以外的层的氮化物膜，所述最外层由氧化物膜或 氧氮化物膜并且具有接触半导体衬底，栅氧化物膜或除氮化物膜之外的侧壁间隔物层的底表面。 半导体器件可以进一步包括具有三层或更多层并且形成在叠层栅电极结构的侧壁上的第二叠层侧壁间隔体，第二叠层侧壁间隔体包括作为不接触半导体衬底的中间层的氮化物膜。 还提供了将存储区域和逻辑区域集成在同一衬底上，两个区域中的电极呈现如上所述的侧壁间隔物。 还提供了用于制造这种装置的方法。

公开(公告)号：EP1986240A2

公开(公告)日：2008-10-29

申请号：EP08162077.5

申请日：2003-10-23

Applicant: Fujitsu Limited

Inventor： Anezaki, Toru, Fujitsu Limited

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L21/8247 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8239 ,  H01L27/105

CPC classification number: H01L21/823462 ,  H01L21/2652 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two or more layers and formed on side walls of the gate electrode, the first laminated side wall spacers including a nitride film as a layer other than an outermost layer, the outermost layer being made of an oxide film or an oxynitride film and having a bottom surface contacting the semiconductor substrate, the gate oxide film or a side wall spacer layer other than the nitride film. The semiconductor device may further comprise second laminated side wall spacers having three or more layers and formed on side walls of a laminated gate electrode structure, the second laminated side wall spacers including a nitride film as an intermediate layer not contacting the semiconductor substrate.

Abstract translation: 提供了具有隔离功能的绝缘膜侧壁间隔物的半导体器件。 半导体器件包括：栅极氧化膜和形成在半导体衬底上方的栅电极; 形成在半导体衬底中的源/漏区; 以及形成在所述栅电极的侧壁上的具有两层以上的层的第一层叠侧壁隔壁，所述第一层叠侧壁隔板包括作为除了最外层之外的层的氮化膜，所述最外层由氧化膜或 氧氮化物膜，并且具有与半导体衬底，栅极氧化物膜或除了氮化物膜之外的侧壁间隔层接触的底表面。 半导体器件还可以包括具有三层或更多层并且形成在层叠栅电极结构的侧壁上的第二层叠侧壁间隔物，第二层叠侧壁间隔物包括不与半导体衬底接触的中间层的氮化物膜。 还提供了存储区域和逻辑区域在同一衬底上的集成，两个区域中的电极呈现如上所述的侧壁间隔物。 还提供了一种用于制造这种装置的方法。