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    DELTA SIGMA MODULATOR AND MODULATION METHOD THEREOF
    32.
    发明公开
    DELTA SIGMA MODULATOR AND MODULATION METHOD THEREOF 审中-公开
    DELTA SIGMA调制器及其调制方法

    公开(公告)号：EP2983296A1

    公开(公告)日：2016-02-10

    申请号：EP14795481.2

    申请日：2014-04-03

    申请人： ZTE Corporation

    发明人： DONG, Peng ,  LIAO, Hongyin

    IPC分类号： H03M3/00

    CPC分类号： H03M7/3033

    摘要： A delta sigma modulator (DSM) and a method for the DSM performing modulation, wherein, the method includes: pre-processing inputted data; predicting a DSM modulation result according to the current data; finally, performing a DSM modulation on the current data according to the pre-processed data and the prediction result. An embodiment of the present invention pre-processes the inputted data and predicts a DSM modulation result so as to realize a multistage pipeline register structure in DSM, thus improving timing sequences of key sections such as adders without affecting characteristics of an original transfer function, thereby increasing sampling frequency of circuit operations and improving SNR performance.

    摘要翻译： 一种Δ-Σ调制器（DSM）和一种用于DSM执行调制的方法，其中，所述方法包括：预处理输入的数据; 根据当前数据预测DSM调制结果; 最后根据预处理数据和预测结果对当前数据进行DSM调制。 本发明实施例对输入数据进行预处理并预测DSM调制结果，以实现DSM中的多级流水线寄存器结构，从而在不影响原始传输函数的特性的情况下，改善了加法器等关键部分的时序， 增加电路操作的采样频率并提高SNR性能。

    Noise shaping circuits and methods with feedback steering overload compensation and systems using same
    33.
    发明公开
    Noise shaping circuits and methods with feedback steering overload compensation and systems using same 审中-公开
    噪声整形与反馈导向超载补偿和系统，使电路和方法

    公开(公告)号：EP1890384A2

    公开(公告)日：2008-02-20

    申请号：EP07121550.3

    申请日：2003-08-01

    申请人： Cirrus Logic, Inc.

    发明人： Melanson, Johan Laurence

    IPC分类号： H03M7/00 ,  H03M3/04

    CPC分类号： H03M7/3011 ,  H03M7/3026 ,  H03M7/3033

    摘要： A noise shaper comprising a first feedback loop (306, 305, 301, 303) for noise shaping a first feedback signal under normal operating conditions including a first filter (301) having a first signal transfer function, a second feedback loop (308, 307, 302) that is stable under overload conditions and includes a second filter (208, 302) having a second signal transfer function differing from the first signal transfer function, a quantizer (303) having an input responsive to output of the first feedback loop, a limiter (309) having an input responsive to the outputs of the quantizer (303) and the second feedback loop, and steering circuitry (312, 309, 304, 303) for steering feedback from an output of the limiter (309) to inputs of the first and second feedback loops.The steering circuitry including a first output for providing the first feedback signal to the first feedback loop and a second output for providing a second feedback signal to the second feedback loop.

    摘要翻译： 噪声整形器包括用于噪声的第一反馈环路（306，305，301，303）成形正常操作条件下，包括第一过滤器（301），具有第一信号传递函数，第二反馈回路（308，307下的第一反馈信号 ，302）确实是过载的条件下是稳定的，并且包括具有第二信号传递函数从所述第一信号传递函数不同的第二滤波器（208，302），其具有用于输入量化器（303）响应于第一反馈环路的输出， 具有输入响应于所述量化器（303）和所述第二反馈回路，和导向电路（312，309，304，303），用于从在所述限幅器（309）的输出转向反馈的输出的限幅器（309），以输入 的第一和第二反馈loops.The导向电路包括用于提供所述第一反馈信号到所述第一反馈回路和用于向第二反馈回路提供第二反馈信号的第二输出的第一输出。

    Signal processor for 1-bit signals, comprising a nth order Delta-Sigma modulator
    36.
    发明公开
    Signal processor for 1-bit signals, comprising a nth order Delta-Sigma modulator 失效
    1比特信号信号处理器与Σ-Δ调制器阶数n的

    公开(公告)号：EP0845867A3

    公开(公告)日：2000-03-29

    申请号：EP97308704.2

    申请日：1997-10-30

    申请人： Sony United Kingdom Limited

    发明人： Eastty, Peter Charles ,  Sleight, Christopher ,  Thorpe, Peter Damien

    IPC分类号： H03M7/00

    CPC分类号： H03M7/3033 ,  H03M7/3028 ,  H03M7/304

    摘要： A signal processor for 1-bit signals comprises a fifth order Delta-Sigma Modulator (DSM) having an input 4 for receiving a 1-bit signal and an output 5 at which a processed 1-bit signal is produced by a quantizer Q. The quantizer Q receives a p-bit signal from a series of 5 signal integration stages. Each stage comprises a first 1-bit multiplier An coupled to the input 4, a second 1-bit multiplier Cn coupled to the output 5, an adder 6n which sums the outputs of the coefficient multipliers and an integrator 7n which integrates the output of the adder 6n. A final stage comprises a coefficient multiplier An+1 and an adder 6n+1. The adder 6n+1 sums the output of the coefficient multiplier An+1 and the output of the integrator of the preceding integration stage. The coefficients An and Cn are chosen to provide an overall attenuation of the input signal and of the quantization noise produced by the quantizer and also to provide a low pass filter which provides a compensating gain to the input signal. In this way the quantization noise outside the band of the input signal is reduced. Reduction of quantization noise enhances stability of the circuit and also allows several DSMs to be connected in series by preventing the build-up of excess noise which may compromise stability.

    Signal processor for 1-bit signals, comprising a nth order Delta-Sigma modulator
    37.
    发明公开
    Signal processor for 1-bit signals, comprising a nth order Delta-Sigma modulator 失效
    SignalProzessorenfür1-Bit-Signale mit Sigma-Delta-Modulatoren n-ter Ordnung

    公开(公告)号：EP0845867A2

    公开(公告)日：1998-06-03

    申请号：EP97308704.2

    申请日：1997-10-30

    申请人： Sony United Kingdom Limited

    发明人： Eastty, Peter Charles ,  Sleight, Christopher ,  Thorpe, Peter Damien

    IPC分类号： H03M7/00

    CPC分类号： H03M7/3033 ,  H03M7/3028 ,  H03M7/304

    摘要： A signal processor for 1-bit signals comprises a fifth order Delta-Sigma Modulator (DSM) having an input 4 for receiving a 1-bit signal and an output 5 at which a processed 1-bit signal is produced by a quantizer Q. The quantizer Q receives a p-bit signal from a series of 5 signal integration stages. Each stage comprises a first 1-bit multiplier An coupled to the input 4, a second 1-bit multiplier Cn coupled to the output 5, an adder 6n which sums the outputs of the coefficient multipliers and an integrator 7n which integrates the output of the adder 6n. A final stage comprises a coefficient multiplier An+1 and an adder 6n+1. The adder 6n+1 sums the output of the coefficient multiplier An+1 and the output of the integrator of the preceding integration stage. The coefficients An and Cn are chosen to provide an overall attenuation of the input signal and of the quantization noise produced by the quantizer and also to provide a low pass filter which provides a compensating gain to the input signal. In this way the quantization noise outside the band of the input signal is reduced. Reduction of quantization noise enhances stability of the circuit and also allows several DSMs to be connected in series by preventing the build-up of excess noise which may compromise stability.

    摘要翻译： 用于1比特信号的信号处理器包括具有用于接收1比特信号的输入4的第五级ΔΣ调制器（DSM）和由量化器Q产生经处理的1比特信号的输出5。 量化器Q从一系列5个信号积分级接收p位信号。 每个级包括耦合到输入端4的第一个1位乘法器A，耦合到输出端5的第二个1位乘法器Cn，将系数乘法器的输出相加的加法器6n和积分器7n， 加法器6n。 最后一级包括系数乘法器An + 1和加法器6n + 1。 加法器6n + 1将系数乘法器An + 1的输出和前一积分级的积分器的输出相加。 选择系数An和Cn以提供输入信号和由量化器产生的量化噪声的总体衰减，并且还提供向输入信号提供补偿增益的低通滤波器。 以这种方式，减小输入信号频带外的量化噪声。 量化噪声的降低提高了电路的稳定性，并且还允许通过防止可能损害稳定性的过量噪声的累积来串联多个DSM。