利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.011 秒)

    Signal processing apparatus and method for sound field processing of sigma-delta modulated digital signal
    1.
    发明公开
    Signal processing apparatus and method for sound field processing of sigma-delta modulated digital signal 失效
    对Σ-Δ的声场处理的信号处理装置和方法调制的数字信号

    公开(公告)号：EP0821491A3

    公开(公告)日：1999-09-29

    申请号：EP97305525.4

    申请日：1997-07-23

    申请人： SONY CORPORATION

    发明人： Noguchi, Masayoshi ,  Ichimura, Gen

    IPC分类号： H03M7/00

    CPC分类号： H03M7/3013

    摘要： A signal processing method and apparatus in which, for limiting a ΣΔ modulated 1-bit digital signal for amplitude limitation, the 1-bit digital signal is temporarily converted into a multi-bit signal. For re-quantizing the converted multi-bit signal, an integrator constituting a ΣΔ re-modulator is controlled by a limiter. This enables the 1-bit digital signal to be amplitude-controlled in the form of the digital signal without converting the 1-bit digital signal into an analog signal.

    Improved analog signal generation using a delta-sigma modulator
    3.
    发明公开
    Improved analog signal generation using a delta-sigma modulator 有权
    Verbesserte Analogsignalerzeugung mittels eines Delta-Sigma Modulators

    公开(公告)号：EP1624577A1

    公开(公告)日：2006-02-08

    申请号：EP04103817.5

    申请日：2004-08-06

    申请人： Agilent Technologies, Inc.

    发明人： Rivoir, Jochen

    IPC分类号： H03M3/00

    CPC分类号： H03M7/3013 ,  H03M3/344 ,  H03M3/50 ,  H03M7/3024 ,  H03M7/3031

    摘要： The present invention relates to a method and a system for generating an analog signal x(t) based on samples x[k] representing said analog signal, said method comprising the step of feeding said samples x[k] into a delta-sigma modulator (552 689), said delta-sigma modulator (552; 689) outputting a sequence of bits q[k], said method being characterized by the step of a non-linear time-discrete function into a feedback loop between a quantizer element (509; 691) and a delta element (506; 606) of said delta-sigma modulator (552; 689), wherein arguments of said non-linear time-discrete function comprise a current bit and at least one bit previous to said current bit.

    摘要翻译： 本发明涉及一种基于表示所述模拟信号的样本x [k]产生模拟信号x（t）的方法和系统，所述方法包括将所述采样x [k]馈送到Δ-Σ调制器 （552,689），所述Δ-Σ调制器（552; 689）输出比特序列q [k]，所述方法的特征在于将非线性时间离散函数转换为量化器元件（ 509; 691）和所述Δ-Σ调制器（552; 689）的δ元件（506; 606），其中所述非线性时间离散函数的参数包括当前位和在所述当前位之前的至少一个位 。

    digital signal processing method and apparatus
    4.
    发明公开
    digital signal processing method and apparatus 失效
    Vorrichtung und Verfahren zur digitalen Signalverarbeitung

    公开(公告)号：EP0783207A3

    公开(公告)日：1999-03-24

    申请号：EP96309281.2

    申请日：1996-12-19

    申请人： SONY CORPORATION

    发明人： Noguchi, Masayoshi ,  Ichimura, Gen

    IPC分类号： H03M7/00

    CPC分类号： H03M7/3013

    摘要： A digital signal processing method and apparatus in which no noise is produced when switching between an original sigma-delta modulated signal and a sigma-delta re-modulated signal obtained on sigma-delta modulation of the original sigma-delta modulated signal. In a digital signal processing device 1, delay line 3 delays the original sigma-delta modulated signal from an input terminal 2 by a pre-set number of samples. A sigma-delta modulator 6 sets the first-stage feedback loop to next stage feedback loop gain ratio to an integer and outputs a sigma-delta re-modulated signal. A bit length converter 5 matches the amplitude level of the original sigma-delta modulated signal entering the sigma-delta modulator 6 to the amplitude level of a feedback signal to a first-stage integrator employed in the sigma-delta modulator 6. On reception of a switching control signal S D from an input terminal 7, the digital signal processing device 1 causes a pattern coincidence detector 28 to detect pattern coincidence between the original 1-bit signal S A delayed by the delay line 3, having a number of taps corresponding to the gain ratio, and a sigma-delta re-modulated 1-bit signal S B , to output a detection signal S T . This allows a switching controller 29 to control switching of a changeover switch 4 to output a signal changed over from S A to S B at an output terminal 8.

    摘要翻译： 一种数字信号处理方法和装置，当在原始Σ-Δ调制信号与在原始Σ-Δ调制信号的Σ-Δ调制之间获得的Σ-Δ重新调制信号之间进行切换时，不产生噪声。 在数字信号处理装置1中，延迟线3将来自输入端2的原始Σ-Δ调制信号延迟预定数量的采样。 Σ-Δ调制器6将第一级反馈环路设置为下一级反馈环路增益比至整数，并输出Σ-Δ重新调制信号。 比特长度转换器5使进入Σ-Δ调制器6的原始Σ-Δ调制信号的幅度电平与反馈信号的幅度电平匹配到在Σ-Δ调制器6中采用的第一级积分器。 来自输入端子7的开关控制信号SD，数字信号处理装置1使模式一致检测器28检测由延迟线3延迟的原始1位信号SA之间的模式一致性，具有对应于 增益比和Σ-Δ再调制1比特信号SB，以输出检测信号ST。 这允许切换控制器29控制切换开关4的切换，以在输出端子8处输出从SA切换到SB的信号。

    Audio signal processor
    6.
    发明公开
    Audio signal processor 有权
    音频信号处理器

    公开(公告)号：EP0911979A3

    公开(公告)日：2002-07-17

    申请号：EP98308005.2

    申请日：1998-10-01

    申请人： Sony United Kingdom Limited

    发明人： Eastty, Peter Charles ,  Thorpe, Peter Damien ,  Sleight, Christopher

    IPC分类号： H03M7/50 ,  G06F7/556 ,  H03M3/02

    CPC分类号： H03M7/3013 ,  G06F7/556

    摘要： An audio signal processor for processing 1-bit signals, comprises an input (40) for receiving a 1-bit signal, means (41,42) for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means (43) for determining the absolute value of the n-bit signal, means (46,51) for producing a dynamics control signal dependent on the said absolute value, means (48) for applying the dynamics control signal to the 1-bit input signal, and means (49) for requantizing the dynamics controlled signal as a 1-bit signal and shaping the noise in the requantised 1-bit signal. Circuits for producing LOG base 2 and the corresponding anti-log are also disclosed.

    digital signal processing method and apparatus
    7.
    发明公开
    digital signal processing method and apparatus 失效
    装置和方法，用于数字信号处理

    公开(公告)号：EP0783207A2

    公开(公告)日：1997-07-09

    申请号：EP96309281.2

    申请日：1996-12-19

    申请人： SONY CORPORATION

    发明人： Noguchi, Masayoshi ,  Ichimura, Gen

    IPC分类号： H03M7/00

    CPC分类号： H03M7/3013

    摘要： A digital signal processing method and apparatus in which no noise is produced when switching between an original sigma-delta modulated signal and a sigma-delta re-modulated signal obtained on sigma-delta modulation of the original sigma-delta modulated signal. In a digital signal processing device 1, delay line 3 delays the original sigma-delta modulated signal from an input terminal 2 by a pre-set number of samples. A sigma-delta modulator 6 sets the first-stage feedback loop to next stage feedback loop gain ratio to an integer and outputs a sigma-delta re-modulated signal. A bit length converter 5 matches the amplitude level of the original sigma-delta modulated signal entering the sigma-delta modulator 6 to the amplitude level of a feedback signal to a first-stage integrator employed in the sigma-delta modulator 6. On reception of a switching control signal S D from an input terminal 7, the digital signal processing device 1 causes a pattern coincidence detector 28 to detect pattern coincidence between the original 1-bit signal S A delayed by the delay line 3, having a number of taps corresponding to the gain ratio, and a sigma-delta re-modulated 1-bit signal S B , to output a detection signal S T . This allows a switching controller 29 to control switching of a changeover switch 4 to output a signal changed over from S A to S B at an output terminal 8.