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41 条记录 (耗时 0.014 秒)

    CYCLE-EFFICIENT TDM TIMESLOT REMAPPING FOR NETWORK PROCESSING ENGINES
    31.
    发明授权
    CYCLE-EFFICIENT TDM TIMESLOT REMAPPING FOR NETWORK PROCESSING ENGINES 有权
    CYCLE高效TDM ZEITSCHLITZNEUZUWEISUNG处理网络引擎

    公开(公告)号：EP1695472B1

    公开(公告)日：2008-07-16

    申请号：EP04811448.2

    申请日：2004-11-17

    申请人： Intel Corporation

    发明人： BORKOWSKI, Daniel ,  BORKOWSKI, Nancy

    IPC分类号： H04J3/16 ,  H04L12/56

    CPC分类号： H04L49/901 ,  H04J3/1635 ,  H04L49/90

    摘要： A method and apparatus for remapping channel data are presented. Multiple successive frames carrying data in timeslots are received. The timeslots are assigned to channels so that data for the channels includes interleaved data. The data from the multiple successive frames for each of a predetermined number of the timeslots are aggregated. The aggregated data is mapped, by timeslot, in the order that the data is aggregated, to produce a timeslot-based map. The aggregated data of the timeslot-based map is remapped to produce a channel-based map in which the data for the channels are grouped together by channel in the order that the data were received.

    Method and apparatus for interfacing a parallel connection
    33.
    发明公开
    Method and apparatus for interfacing a parallel connection 审中-公开
    用于连接的并联连接的方法和装置

    公开(公告)号：EP1274207A3

    公开(公告)日：2006-08-16

    申请号：EP02291511.0

    申请日：2002-06-18

    申请人： ALCATEL

    发明人： Cucchi, Silvio ,  Ronchetti, Luigi ,  Costantini, Carlo

    IPC分类号： H04L25/14

    CPC分类号： H04L1/0065 ,  H04J3/1611 ,  H04J3/1635 ,  H04L25/14 ,  Y10S370/907

    摘要： A method and apparatus for interfacing a parallel connection, the parallel connection transmitting high bit-rate signals for a short distance. The method comprises: receiving a synchronous N-bits input data flow at a first input frequency; inserting said input data flow into parallel packets having a given length; and outputting said packets having a given length at a second output frequency onto a M-wires parallel connection. The method further comprises the steps of: defining an elementary packet comprising M lines and B+1 columns; defining a parallel packet by employing an integer number of said elementary packets, said number of elementary packets being chosen in order to maintain a constant phase relationship between the input frequency and the output frequency according to a number of parity lines in the elementary packet and to a code factor onto the parallel connection; inserting the input data flow into said parallel packet; and sending said parallel packet with the input data flow inserted therein into said parallel connection.

    Method and system for protocol conversion
    35.
    发明公开
    Method and system for protocol conversion 审中-公开
    Verfahren und Vorrichtung zurProtokollübersetzung

    公开(公告)号：EP1213878A2

    公开(公告)日：2002-06-12

    申请号：EP01403117.3

    申请日：2001-12-05

    申请人： ALCATEL

    发明人： Johan, Ronald ,  Underwood, Grant James ,  Leece, Philip Donald

    IPC分类号： H04L12/28 ,  H04L29/06

    CPC分类号： H04M11/062 ,  H04J3/125 ,  H04J3/1635 ,  H04L12/2801 ,  H04L69/08 ,  H04Q11/04 ,  H04Q2213/13003 ,  H04Q2213/13039 ,  H04Q2213/13196 ,  H04Q2213/13204 ,  H04Q2213/13213 ,  H04Q2213/13216 ,  H04Q2213/13292 ,  H04Q2213/1332

    摘要： This invention enables various types of equipment using different protocols to be multiplexed on to a two-wire line carrying traffic with a predetermined protocol. Transmissions from equipment which uses separate information and signalling channels are multiplexed on to a single channel of the predetermined protocol with the signalling incorporated in to the channel by the use of bit-robbing techniques.
    This enables several different types of equipment to be connected via a single pair to the network access point, permitting standardization of the line cards in the access equipment.

    摘要翻译： 本发明使得使用不同协议的各种类型的设备被复用到具有预定协议的携带业务的双线路上。 使用单独的信息和信令信道的设备的传输被复用到预定协议的单个信道上，信令通过使用比特抢占技术结合到信道中。 这使得几种不同类型的设备可以通过一对连接到网络接入点，从而允许接入设备中的线路卡标准化。

    ADDED BIT SIGNALLING IN A TELECOMMUNICATIONS SYSTEM
    36.
    发明公开
    ADDED BIT SIGNALLING IN A TELECOMMUNICATIONS SYSTEM 失效
    附加的信令比特NEWS在传输系统

    公开(公告)号：EP0702869A4

    公开(公告)日：1998-04-22

    申请号：EP94919996

    申请日：1994-05-10

    申请人： ADC TELECOMMUNICATIONS INC

    发明人： WADMAN MARK S ,  OPOCZYNSKI ADAM ,  ELPERS MARK D

    IPC分类号： H04J3/06 ,  H04J3/12 ,  H04J3/14 ,  H04J3/16 ,  H04L7/08 ,  H04J3/07

    CPC分类号： H04J3/14 ,  H04J3/0605 ,  H04J3/12 ,  H04J3/1635

    摘要： A telecommunication system includes an added bit signalling method and apparatus for conveying signalling information between a head end (300) and multiple remote ends (500) connected over a passive distribution network. In accordance with the present invention, an added bit (NB) having an identifiable data sequence patterned thereon is appended to each channel within a succession of frames. The present invention therefore appends an added-bit sequence to each channel such that each channel sample carries its own multiframe and alignment information. The remote ends monitor the added bits to locate multiframing and alignment information and to identify individual time slots within each frame. The added bit can be further utilized for out-of-band signalling or to provide an additional data links.

    Interface device for format conversion
    37.
    发明公开
    Interface device for format conversion 失效
    Formatumwandlungsschnittstelleanordnung。

    公开(公告)号：EP0622919A1

    公开(公告)日：1994-11-02

    申请号：EP94105926.3

    申请日：1994-04-16

    申请人： ALCATEL N.V.

    发明人： Amengual Guedan, Juan ,  Menendez Martin, Ana Ma. del Mar

    IPC分类号： H04J3/16

    CPC分类号： H04J3/1635

    摘要： Of the type that performs a conversion between input data streams and standard interfaces with the same information rate.
    The device comprises a first line receiver (RX1) for a first input data stream that detects errors in the received stream and an interface converter (IC1) that suppresses the bits in it not carrying information and performs the interface conversion. It also comprises a second interface converter (IC2) and a line transmitter (TX1) for conversion in the opposite direction.
    It also includes a second line receiver (RX2) for a second input data stream that detects the errors in the received stream, a memory module (MM1) where various frames of the incoming interface are stored in the addresses indicated by a memory control module (MCM), such that reading this sequentially generates the equivalent standard type interfaces. There is another memory module (MM2) and another line transmitter (TX2) that perform the conversion in the opposite direction.

    摘要翻译： 执行输入数据流与具有相同信息速率的标准接口之间转换的类型。 该装置包括用于检测接收到的流中的错误的第一输入数据流的第一行接收器（RX1）和抑制其中不承载信息并执行接口转换的位的接口转换器（IC1）。 它还包括用于在相反方向转换的第二接口转换器（IC2）和线路发送器（TX1）。 它还包括用于检测接收到的流中的错误的第二输入数据流的第二行接收器（RX2），存储器模块（MM1），其中输入接口的各种帧存储在由存储器控制模块指示的地址 MCM），使得读取顺序生成等效的标准类型接口。 还有另一个存储器模块（MM2）和另一个线路发送器（TX2），以相反方向执行转换。

    Format converter
    39.
    发明公开
    Format converter 失效
    Formatumsetzer。

    公开(公告)号：EP0383437A2

    公开(公告)日：1990-08-22

    申请号：EP90300615.3

    申请日：1990-01-22

    申请人： DATA GENERAL CORPORATION

    发明人： Almond, Gary Robert ,  Nobile, Daniel Alexander

    IPC分类号： H04J3/16

    CPC分类号： H04J3/1635 ,  G05B2219/31174

    摘要： Format Conversion is performed between bit streams which embed sub-rate circuit data according to different protocols. The system (1) locates and extracts the sub-­rate circuit data embedded, in an input serial bit stream, in accordance with a first predefined protocol, (2) aligns the data in a buffer, and (3) creates an output bit stream in which the extracted circuit data is reformatted and inserted in accordance with a second predefined protocol. A programmable bit map driven format conversion module operates the data aligned in the aforementioned buffer. The conversion process is bidirectional and illustratively facilitates conversion between a single stage time division multiplexed data format and a two stage time division multiplexed format (e.g. X.50 and I.463), or, more generally, between any two predefined protocols. The system permits great flexibility in network system configuration and permits multiple channels of different format or frame alignments to be converted simultaneously.

    摘要翻译： 在根据不同协议嵌入子速率电路数据的比特流之间执行格式转换。 系统（1）根据第一预定义协议定位并提取在输入串行比特流中嵌入的子速率电路数据，（2）将缓冲器中的数据对齐，（3）创建输出比特流 其中根据第二预定义协议对所提取的电路数据进行重新格式化和插入。 可编程位图驱动格式转换模块操作在上述缓冲器中对齐的数据。 转换过程是双向的，并且示例性地有助于在单级时分复用数据格式和两级时分复用格式（例如X.50和I.463）之间的转换，或者更一般地，在任何两个预定义的协议之间的转换。 该系统允许在网络系统配置中具有很大的灵活性，并允许同时转换不同格式或帧对准的多个通道。

    Data Format converter
    40.
    发明公开
    Data Format converter 失效
    数据格式转换器。

    公开(公告)号：EP0150940A2

    公开(公告)日：1985-08-07

    申请号：EP85300208.7

    申请日：1985-01-11

    申请人： NORTHERN TELECOM LIMITED

    发明人： Steierman, Herbert Lawrence

    IPC分类号： H04J3/18 ,  H04J3/04

    CPC分类号： H04J3/1635 ,  H04J3/047

    摘要： The conversion of bit-interleaved to byte-interleaved data is achieved using a memory (11) and a universal shift register (14). The period of each bit-interleaved timeslot is divided into three parts for which corresponding timing signals are provided. During the first timing signal, the content of a memory location corresponding to an output channel is loaded into the universal shift register (14). During the second timing signal, the incoming bit associated with the timeslot is shifted serially into the register (14) and during the third signal, the content of the register (14) is returned to its original location in the memory (11). After a frame of bit-interleaved data has been received at the register (14), the memory (11) contains the corresponding frame of byte-interleaved data.