Simplified planarization process for polysilicon-filled trenches
    31.
    发明公开
    Simplified planarization process for polysilicon-filled trenches 失效
    多晶硅填充沟槽简体平坦化工艺。

    公开(公告)号:EP0166207A2

    公开(公告)日:1986-01-02

    申请号:EP85106318.0

    申请日:1985-05-23

    IPC分类号: H01L21/76

    摘要: The method of planarizing polysilicon-filled trenches involves first filling the trenches (12) with an undoped polysilicon (14) until the upper surface (18) is substantially planar. The polycrystalline silicon (14) is then heavily doped by means of diffusion of a dopant from the upper surface. The time and temperature of the diffusion are carefully controlled providing for the dopant to penetrate the polysilicon to a depth (16), level with the tops of the trenches. A selective etchant is then utilized which removes the heavily doped polysilicon (16) and leaves the undoped polysilicon (17) untouched in the trenches (12).

    Transistor having emitter self-aligned with an extrinsic base contact and method of making it
    32.
    发明公开
    Transistor having emitter self-aligned with an extrinsic base contact and method of making it 失效
    具有晶体管,相对于所述外部基极接触的自对准发射器和制造方法。

    公开(公告)号:EP0096155A2

    公开(公告)日:1983-12-21

    申请号:EP83101750.4

    申请日:1983-02-23

    IPC分类号: H01L21/285 H01L29/08

    摘要: A vertical bipolar transistor structure has an extrinsic base region (4) covered by a metal silicide (eg WSi 2 ) layer (6) and a doped (eg with boron) polysilicon layer (7). The metal silicide and polysilicon layers (6, 7) have an opening therein with which the emitter (3) and intrinsic base region (2) of the transistor are aligned.
    The vertical bipolar transistor structure can be produced by a method including delimiting a transistor area in a semiconductor substrate, depositing in succession over the the transistor area a silicide layer (6), a doped polysilicon layer (7) and a silicon dioxide layer (8), forming an aperture through the silicon dioxide, the doped polysilicon and the silicide layers, forming an insulating layer (8A) over the transistor area and driving in dopant from the polysilicon layer to form an extrinsic base region (4), removing the insulating layer from the base of the aperture but not from the sidewall of the aperture and forming an intrinsic base region and an emitter aligned with the aperture and the extrinsic base region.

    摘要翻译: 一种垂直双极晶体管结构具有非本征基区(4)通过金属硅化物覆盖的(例如WSi2)层(6)和一个掺杂的(例如,用硼)的多晶硅层(7)。 金属硅化物层和多晶硅层(6,7)在开口在其中具有与该发射器(3)和本征基极区域(2)晶体管的排列。 ... 垂直双极晶体管结构可以通过包括在半导体衬底限定的晶体管区,陆续在该晶体管的区域上沉积的硅化物层的方法来制造(6),掺杂的多晶硅层(7)和一个 二氧化硅层(8);形成在通过所述二氧化硅,掺杂的多晶硅和硅化物层孔,在晶体管区域的绝缘层(图8A)的形成和从多晶硅层中的掺杂剂驱动以在非本征基极区(4 ),从孔的底部而不是从所述孔的所述侧壁去除所述绝缘层和本征基极区和与所述孔和所述非本征基区对准发射极的形成。