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208 条记录 (耗时 0.015 秒)

    Improvements in or relating to semiconductor devices
    7.
    发明公开
    Improvements in or relating to semiconductor devices 失效
    半导体器件或与之相关的改进

    公开(公告)号：EP0813239A1

    公开(公告)日：1997-12-17

    申请号：EP97102734.7

    申请日：1997-02-20

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Chatterjee, Amitava ,  Houston, Theodore W. ,  Chen, Ih-Chin ,  Esquirel, Agerico L. ,  Nag, Somnath ,  Ali, Iqbal ,  Joyner, Keith A. ,  Hu, Yin ,  McKee, Jeffrey A. ,  McAnally, Peter S.

    IPC分类号： H01L21/762 ,  H01L21/3105

    CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

    摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

    摘要翻译： 生产半导体器件或集成电路的技术产生平坦化的填充层，其在抛光之后具有更均匀的厚度，例如通过化学机械抛光（CMP）。 虚拟有效区域插入衬底的通常会被场氧化物占据的部分中的有源区域之间，以便减少在CMP期间在这些区域发生的“凹陷”。 伪有效区域可以采取大块的形状，部分或完全形成的环形结构或多个支柱，其面积密度可被调节以匹配衬底的该区域中的有源区域的面积密度。 柱子的设计规则可以是这样的，即在多晶硅线或第一级金属化线要放置的位置不放置柱子以避免寄生电容。

    Semiconductor device and method of producing same
    8.
    发明公开
    Semiconductor device and method of producing same 失效
    Halbleiteranordnung und Verfahren zu seiner Herstellung

    公开(公告)号：EP0798776A2

    公开(公告)日：1997-10-01

    申请号：EP97302035.7

    申请日：1997-03-25

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Egawa, Hidemitsu

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76237 ,  Y10S148/05

    摘要： A trench 13 is formed to isolate a first region 11a and a second region 11b where elements of a semiconductor substrate 11 such as a silicon substrate are formed, and a lamination layer of a first silicon oxide layer 14 having a silicon excess stoichiometry (SiO x ; 2 2 ) having an equilibrium composition is filled in the trench 13. The second silicon oxide layer is hydrated. In addition, by heating the semiconductor substrate 11, the first silicon oxide layer 14 is oxidized into the second silicon oxide layer 15 (SiO 2 ) having an equilibrium composition. At this time, the first silicon oxide layer 14 has its volume expanded while it is oxidized into the second silicon oxide layer 15 having an equilibrium composition, while the second silicon oxide layer 15 is contracted due to dehydration by the heating treatment and removal of a defective lattice. Therefore, the volume expansion of the first silicon oxide layer 14 is offset by the volume contraction of the second silicon oxide layer 15 to reduce extensively a stress to be applied to the semiconductor substrate 11, so that the silicon oxide layer filled in the trench 13 can be densified.

    摘要翻译： 形成沟槽13以隔离第一区域11a和第二区域11b，其中形成诸如硅衬底的半导体衬底11的元件，并且具有硅过量化学计量（SiO x; Si）的第一氧化硅层14的层压层。 2

    Process of fabricating semiconductor device having isolating oxide rising out of groove
    9.
    发明公开
    Process of fabricating semiconductor device having isolating oxide rising out of groove 失效
    一种用于从一个坑具有优异隔离氧化物的制造半导体器件的工艺

    公开(公告)号：EP0782185A2

    公开(公告)日：1997-07-02

    申请号：EP96120807.1

    申请日：1996-12-23

    申请人： NEC CORPORATION

    发明人： Abiko, Hitoshi

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76224 ,  Y10S148/05

    摘要： When an isolating oxide (15c) is formed in a silicon substrate (11), a side wall (14a) is formed on the inner wall of a mask (14a) consisting of a lower silicon oxide layer (12a) and an upper silicon nitride layer (12b) for forming a groove (11a) in the silicon substrate (11) in such a manner as to be laterally spaced from the inner wall of the upper silicon nitride layer (12b), and the isolating oxide (15c) is formed from a silicon oxide layer deposited over the mask (12b) after removal of the side wall (14a) by using a polishing, thereby preventing the isolating oxide (15c) from undesirable side etching during an etching step for the lower silicon oxide layer (12a).