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    GAS PHASE DOPING OF SEMICONDUCTOR MATERIAL IN A COLD-WALL RADIANTLY HEATED REACTOR UNDER REDUCED PRESSURE.
    1.
    发明公开
    GAS PHASE DOPING OF SEMICONDUCTOR MATERIAL IN A COLD-WALL RADIANTLY HEATED REACTOR UNDER REDUCED PRESSURE. 失效
    气相约会由半导体材料在低压下与冷却壁，辐射加热反应器中。

    公开(公告)号：EP0628213A4

    公开(公告)日：1997-02-19

    申请号：EP93905904

    申请日：1993-02-12

    申请人： PROCESSING TECHNOLOGY INC D B

    发明人： JOHNSGARD KRISTIAN E ,  GALEWSKI CARL ,  KERMANI AHMAD

    IPC分类号： H01L21/00 ,  H01L21/22 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/20 ,  H01L21/223 ,  H01L21/306

    CPC分类号： H01L21/67167 ,  H01L21/2254 ,  H01L21/32155 ,  H01L21/67207 ,  Y10S148/03 ,  Y10S148/035 ,  Y10S438/923

    摘要： A technique for doping silicon (100) material or other semiconductors (100, 200) uses gas phase dopant sources under reduced pressure in a radiantly heated (11), cold-wall reactor (10). The technique is applied to the automated integrated circuit manufacturingtechniques being adopted in modern fabrication facilities. The method includes placing a substrate (20) comprising semiconductor material on a thermally isolated support structure (18, 19) in a reduced pressure, cold-wall (25) reaction chamber (10); radiantly heating (11) the substrate (20) within the reaction chamber (10) to a controlled temperature; flowing a gas phase source of dopant at controlled pressure and concentration in contact with the substrate (20) so that the dopant is absorbed by the substrate (20) and annealing the substrate (20). The substrate (20) may be first coated with a layer of polycrystalline (105) semiconductor, and then gas phase doping as described above may be applied to the polycrystalline layer (105).

    摘要翻译： 一种用于掺杂硅材料或其它半导体技术在辐射加热，冷壁反应器使用减压气相掺杂剂源。 该技术被应用到自动化集成电路制造技术在现代制造设施被采用。 该方法包括：放置一个基片在减压，冷壁反应室上的热隔离的支撑结构，其包括半导体材料; 辐射方式加热所述反应室中以受控的温度内的基片; 在与基材接触受控压力和浓度的掺杂剂流动的气相源所以没掺杂剂是由基板吸收，退火该基材。 基板可以首先涂覆有如上所述的可施加到该多晶层的多晶半导体层，然后气相掺杂。

    Transistor having emitter self-aligned with an extrinsic base contact and method of making it
    4.
    发明公开
    Transistor having emitter self-aligned with an extrinsic base contact and method of making it 失效
    具有自动对准基板触点的发光体的晶体管及其制造方法

    公开(公告)号：EP0096155A3

    公开(公告)日：1984-08-29

    申请号：EP83101750

    申请日：1983-02-23

    申请人： International Business Machines Corporation

    发明人： Isaac, Randall Duane ,  Ning, Tak Hung

    IPC分类号： H01L21/285 ,  H01L29/08

    CPC分类号： H01L29/66272 ,  H01L21/28518 ,  H01L29/1004 ,  Y10S148/035

    摘要： A vertical bipolar transistor structure has an extrinsic base region (4) covered by a metal silicide (eg WSi 2 ) layer (6) and a doped (eg with boron) polysilicon layer (7). The metal silicide and polysilicon layers (6, 7) have an opening therein with which the emitter (3) and intrinsic base region (2) of the transistor are aligned. The vertical bipolar transistor structure can be produced by a method including delimiting a transistor area in a semiconductor substrate, depositing in succession over the the transistor area a silicide layer (6), a doped polysilicon layer (7) and a silicon dioxide layer (8), forming an aperture through the silicon dioxide, the doped polysilicon and the silicide layers, forming an insulating layer (8A) over the transistor area and driving in dopant from the polysilicon layer to form an extrinsic base region (4), removing the insulating layer from the base of the aperture but not from the sidewall of the aperture and forming an intrinsic base region and an emitter aligned with the aperture and the extrinsic base region.

    A method of manufacturing a semiconductor device
    8.
    发明公开
    A method of manufacturing a semiconductor device 失效
    Ein Verfahren zum Herstellen einer Halbleiteranordnung。

    公开(公告)号：EP0476757A2

    公开(公告)日：1992-03-25

    申请号：EP91202331.4

    申请日：1991-09-12

    申请人： Philips Electronics N.V.

    发明人： Josquin, Wilhelmus Jacobus Maria Joseph ,  Peters, Wilhelmus Cornelis Maria ,  van de Goor, Albertus Theodorus Maria

    IPC分类号： H01L21/76 ,  H01L27/082 ,  H01L21/82 ,  H01L21/265 ,  H01L21/033

    CPC分类号： H01L29/66272 ,  H01L21/761 ,  H01L21/82285 ,  Y10S148/035

    摘要： A semiconductor body (1) is provided having a first region (4) of one conductivity type adjacent one major surface (2). An insulating layer (5) is formed on the one major surface and masking means (6,7) are used to form over first and second areas (20 and 21) of the one major surface (2) windows (8,9,10) in the insulating layer (5) through which impurities are introduced to form a relatively highly doped region (11) of the opposite conductivity type adjacent the first area (20) and a relatively lowly doped region (12) of the opposite conductivity type adjacent the second area (21). The surface (5a) of the insulating layer (5) is exposed prior to introducing impurities of the one conductivity type for forming a region (13) within the relatively lowly doped region (12) of the opposite conductivity type and with a dose sufficient to form the region (13) but not sufficient to overdope the relatively highly doped region (11) so avoiding the need to mask the first area (20) during this step. The thickness of the insulating layer (5) is such that a proportion of the impurities of the one conductivity type penetrate the insulating layer (5) to increase the doping of a surface layer (40) of the first region (4) so as to reduce problems such as punch-through effects.

    摘要翻译： 半导体本体（1）具有邻近一个主表面（2）的一个导电类型的第一区域（4）。 绝缘层（5）形成在一个主表面上，并且屏蔽装置（6,7）用于形成一个主表面（2）窗口（8,9,10）上的第一和第二区域（20和21） ）引入绝缘层（5），通过该绝缘层引入杂质以形成与第一区域（20）相邻的相反导电类型的相对高度掺杂的区域（11）以及相邻导电类型相邻的相对低掺杂区域（12） 第二区（21）。 在引入用于形成相对导电类型的相对低掺杂区域（12）内的区域（13）的一种导电类型的杂质之前，绝缘层（5）的表面（5a）被暴露，并且剂量足以 形成区域（13），但不足以过度涂覆相对高掺杂区域（11），从而避免在该步骤期间掩蔽第一区域（20）。 绝缘层（5）的厚度使得一种导电类型的杂质的比例穿透绝缘层（5）以增加第一区域（4）的表面层（40）的掺杂，从而 减少穿透效果等问题。

    Method of Manufacturing a Semiconductor Device
    9.
    发明公开
    Method of Manufacturing a Semiconductor Device 失效
    Halbleitervorrichtung und Verfahren zum Herstellen derselben。

    公开(公告)号：EP0421735A2

    公开(公告)日：1991-04-10

    申请号：EP90310781.1

    申请日：1990-10-02

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Nakasaki, Yasushi, c/o Intellectual Property Div.

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/532

    CPC分类号： H01L23/53233 ,  H01L21/32051 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S148/035 ,  H01L2924/00

    摘要： According to this invention, there is provided to a semiconductor device comprising a semiconductor subst­rate (1) on which an element is formed, an insulating interlayer (9, 10) formed on the semiconductor substrate (11), and a wiring layer (18) having a structure in which a surface of a copper layer (14) in a crystal state is covered with a nitride of a metal not forming an intermetallic compound with copper and the metal and/or the metal nitride is present at grain boundaries of the copper layer (14).

    摘要翻译： 根据本发明，提供了一种半导体器件，包括其上形成有元件的半导体衬底（1），形成在半导体衬底（11）上的绝缘中间层（9,10）和布线层（18）， 具有结晶状态的铜层（14）的表面被不与铜形成金属间化合物的金属的氮化物覆盖，并且金属和/或金属氮化物存在于铜的晶界 层（14）。

    Method of manufacturing a semiconductor device comprising resistors
    10.
    发明公开
    Method of manufacturing a semiconductor device comprising resistors 失效
    制造包含电阻器的半导体器件的方法

    公开(公告)号：EP0159408A3

    公开(公告)日：1987-02-04

    申请号：EP84115903

    申请日：1984-12-20

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Maeda, Takeo c/o Patent Division

    IPC分类号： H01L21/31

    CPC分类号： H01L28/24 ,  Y10S148/035 ,  Y10S148/105 ,  Y10S148/147

    摘要： There is disclosed a method of manufacturing a semiconductor device comprising the steps of forming a polysilicon film (13) on a semiconductor substrate (11) through an oxidation film (12), forming a mask (14) of a predetermined pattern on the polysilicon film, forming a molybdenum film (17) on the polysilicon film and silicifying those regions (18 1 , 18.) of said molybdenum film (17) not covered by the mask so that a structure of the uncovered molybdenum film regions (18 1 , 18 2 ) and those regions (15 1 , 15 2 ) of the polysilicon film located under the uncovered molybdenum regions have low resistance, while a region (16) of the molybdenum film covered by the mask have high resistance.