公开(公告)号：EP1713082A1

公开(公告)日：2006-10-18

申请号：EP06076208.5

申请日：2001-11-21

申请人： Aspex Technology Limited

发明人： Jalowiecki, Ian Paul, Aspex Technology Limited ,  Lancaster, John, Aspex Technology Limited ,  Krikelis, Anargyros, Aspex Technology Limited

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A word organised content-addressable memory (CAM) array for use with an associative data-parallel processor is described. The CAM array comprises a plurality of CAM cells arranged as a series of data words, each cell representing a bit of a word. The CAM cells being interconnected in an interleaved manner to define odd and even alternating cells within a data word and being arranged to provide concurrent read access to multiple bits of data stored in the data word.

摘要翻译： 描述了与关联数据并行处理器一起使用的一个单词组织的内容可寻址存储器（CAM）阵列。 CAM阵列包括被布置为一系列数据字的多个CAM单元，每个单元表示字的位。 CAM单元以交织方式互连以在数据字内定义奇数和偶数交替的单元，并且被布置为向存储在数据字中的多个数据位提供并发读取访问。

公开(公告)号：EP1424698A3

公开(公告)日：2006-05-24

申请号：EP03026973.2

申请日：2003-11-25

申请人： Infineon Technologies AG

发明人： Hatsch, Joel ,  Kamp, Winfried ,  Köppe, Siegmar ,  Künemund, Thomas ,  Söldner, Heinz ,  d'Argouges, Michel

IPC分类号： G11C15/04

CPC分类号： G06F7/02 ,  G06F2207/025 ,  G11C15/04

摘要： Die vorliegende Erfindung stellt eine CAM (content adressable memory) -Vorrichtung bereit, mit: einer ersten Speichereinrichtung (10) mit einem Wortleitungseingang (WL) und mindestens einem Speicherknoten (12; 13) zum Speichern eines ersten Bits eines Datenwortes; einer zweiten Speichereinrichtung (11) mit einem Wortleitungseingang (WL) und mindestens einem Speicherknoten (14; 15) zum Speichern eines zweiten Bits eines Datenwortes; und einer Komparatoreinrichtung (16) zum Vergleichen des ersten und zweiten gespeicherten Bits mit zwei über vier Eingänge (20; 21; 22; 23) zugeführten vorkodierten Vergleichsbits und zum Ansteuern eines Hit-Knoten (17) bei Übereinstimmung des ersten gespeicherten Bits mit dem ersten Vergleichsbit und des zweiten gespeicherten Bits mit dem zweiten Vergleichsbit.

公开(公告)号：EP1657859A1

公开(公告)日：2006-05-17

申请号：EP04772098.2

申请日：2004-08-18

申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

发明人： UGA, M., c/o NTT Intellectual Property Center ,  KURIMOTO, T., c/o NTT Intellectual Property Center ,  AOKI, M., c/o NTT Intellectual Property Center

IPC分类号： H04L12/56 ,  G11C15/04

CPC分类号： H04L45/00 ,  G11C15/00 ,  H04L45/54 ,  H04L45/7453

摘要： A routing table generating unit that generates a routing table describing a next hop to which a packet is to be sent according to a destination address of the packet that is input via an input channel, including a ternary content addressable memory (TCAM); an external memory; a unit that classifies items in information that is received; and a unit that stores an item that uniquely identifies the information among the classified items in the TCAM and stores the rest of the items to the external memory.

摘要翻译： 路由表生成单元，根据通过输入信道输入的分组的目的地地址生成描述要发送分组的下一跳的路由表，所述输入信道包括三元内容可寻址存储器（TCAM）; 外部记忆 对接收到的信息中的项目进行分类的单元; 以及存储在TCAM中的分类项目中唯一地标识信息的项目并将其余的项目存储到外部存储器的单元。

公开(公告)号：EP1557842A3

公开(公告)日：2006-04-12

申请号：EP04019069.6

申请日：2004-08-11

申请人： Hiroshima University

发明人： Koide, Tetsushi ,  Mattausch, Hans Jürgen ,  Yano, Yuji

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： In the present invention, focusing on the point that the number of transistors can be reduced to about 2/5 of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of two of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit (UC), and all of the outputs of the absolute-value-of-difference calculating circuits (UC ij ) for which the number of comparisons thereof are prepared are input to weight comparison circuits (WC ij ), whereby the calculation of the Manhattan distance between the search data (SW) and the reference data (REF) is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.

公开(公告)号：EP1461811B1

公开(公告)日：2006-03-29

申请号：EP02781031.6

申请日：2002-12-05

申请人： Mosaid Technologies Incorporated

发明人： KIM, Jin-Ki ,  VLASENKO, Peter ,  PERRY, Douglas ,  GILLINGHAM, Peter, B.

IPC分类号： G11C15/04

CPC分类号： G11C15/00 ,  G11C15/04

摘要： A low power CAM architecture is disclosed. Matchlines of the CAM array are segmented into a pre search portion and a main search portion. After issuing a search command, a pre search operation is conducted on the pre search portion of the matchline. If the result of the pre search is a match, then the main search is subsequently conducted on the main search portion of the matchline. If the result of pre search is a mismatch, then the main-search is disabled, and consequently there is no power dissipation on the main search portion of the matchlines. Pre search and main search operations can be pipelined to maintain high throughput with minimum latency. Power consumption is further reduced by using a matchline sense circuit for detecting a current on the pre search and main search portions of the matchline. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins, and dummy matchlines are used to generate timed control signals for latching the output of the matchline sense circuits. The matchlines are initially precharged to a miss condition represented by ground potential and are then undergo accelerated precharge to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines to conserve power.

公开(公告)号：EP0905708B1

公开(公告)日：2005-11-16

申请号：EP98307794.2

申请日：1998-09-25

申请人： SUN MICROSYSTEMS, INC.

发明人： Kongetira, Poonacha P.

IPC分类号： G11C15/04

CPC分类号： G11C15/04

公开(公告)号：EP1376607A3

公开(公告)日：2005-09-14

申请号：EP03010546.4

申请日：2003-05-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Park, Chul-Sung

IPC分类号： G11C15/04

CPC分类号： G11C15/04

摘要： A ternary content addressable memory (TCAM) having an array of cells arranged in rows and columns, each cell comprising of a main memory cell for storing a data bit and its complement and a pair of bit lines for carrying the data bit and its complement. A compare circuit having a pair of compare lines and an output node, the compare circuit coupled to the [data]main memory cell for comparing the data bit and its complement with corresponding compare lines and outputting a compared signal at the output node. A match circuit coupled to the output node of the compare circuit and a match input line and a match output line, the match circuit for selectively connecting the match input line to the match output line based on the compared signal. A mask memory cell for storing and outputting mask data and a mask circuit coupled to the match circuit and the match input line and the match output line for masking the compared signal or for selectively connecting the match input line to the match output line based on the mask data.

公开(公告)号：EP1568042A2

公开(公告)日：2005-08-31

申请号：EP03776686.2

申请日：2003-11-12

申请人： Mosaid Technologies Incorporated

发明人： ROTH, Alan ,  MCKENZIE, Robert ,  BECCA, Oswald

IPC分类号： G11C15/00

CPC分类号： G11C15/00 ,  G11C15/04

摘要： A system and method for searching and deleting segmented wide word entries in a CAM array (100) is disclosed. A normal CAM search operation is executed to find the first word segment (102) of a wide word. Once found, a search and delete operation is executed to find all successive word segments (102) of the wide word, with the last word segment (102) being marked as a deleted word segment (102), along a first CAM array direction. Once the last word segment (102) is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment (102). A purge operation is then executed along the opposite CAM array (100) direction to delete all the word segments (102) of the deleted wide word. Match processing circuits (104) in each row of the CAM array (100) can pass search results to an adjacent row (102) above or below it to ensure that only word segments (102) belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

公开(公告)号：EP1557842A2

公开(公告)日：2005-07-27

申请号：EP04019069.6

申请日：2004-08-11

申请人： Hiroshima University

发明人： Koide, Tetsushi ,  Mattausch, Hans Jürgen ,  Yano, Yuji

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： In the present invention, focusing on the point that the number of transistors can be reduced to about 2/5 of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of two of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit (UC), and all of the outputs of the absolute-value-of-difference calculating circuits (UC ij ) for which the number of comparisons thereof are prepared are input to weight comparison circuits (WC ij ), whereby the calculation of the Manhattan distance between the search data (SW) and the reference data (REF) is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.

摘要翻译： 在本发明中，由于由联结存储器的差分绝对值计算电路构成的两个或更多的相关存储器，所以重点在于现有技术中晶体管的数目可以减少到约2/5， 加法电路和位反转电路。 差分绝对值计算电路内置于作为单位比较电路（UC）的全并行型联想存储器中，并且将差分绝对值计算电路（UC ij）的所有输出全部用于 将其比较的数量输入到加权比较电路（WC ij），由此执行搜索数据（SW）和参考数据（REF）之间的曼哈顿距离的计算。 根据该结构，由于可以通过较少数量的晶体管和小面积来实现曼哈顿距离计算电路，所以可以在低功耗和小面积上实现关联存储装置。

公开(公告)号：EP1460640A3

公开(公告)日：2005-05-04

申请号：EP04006654.0

申请日：2004-03-19

申请人： STMicroelectronics Pvt. Ltd

发明人： Srivastavaan, Rajeev ,  Grover, Chiranjeev

IPC分类号： G11C15/04

CPC分类号： G11C15/00

摘要： This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in a first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in a second state of the same clock cycles. The Content Addressable Memory (CAM) architecture (300) comprises an array of CAM cells (303) connected to a compare-data-write-driver (302) and to a read/write block (305), for receiving a compare-data and for reading and/or writing data in the array of CAM cells (303) respectively, outputs of the said CAM cells of said array (303) are coupled to a match block (304) providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during a first state and enabling read-or-write operations within a second state of the same clock cycle in the event of a match.