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    FLASH MEMORY MODULE AND MEMORY SUBSYSTEM
    2.
    发明公开
    FLASH MEMORY MODULE AND MEMORY SUBSYSTEM 审中-公开
    FLASH存储模块和存储子系统

    公开(公告)号：EP2774150A1

    公开(公告)日：2014-09-10

    申请号：EP12845812.2

    申请日：2012-11-01

    申请人： Mosaid Technologies Incorporated

    发明人： KIM, Jin-Ki ,  YI, DaeHee ,  KIM, HyoShin

    IPC分类号： G11C5/06 ,  G11C16/02 ,  G11C7/10

    CPC分类号： G11C5/04 ,  G11C7/1003

    摘要： A mass storage memory module system including a memory module having memory holding members which can be connected to each other, and removably connected to a memory controller. One or more modular memory holding members can be connected to each other to expand the overall storage capacity of the memory module. The presently described expandable memory module does not have a storage capacity limit. A memory holding member includes a plate, a plane, a board and another material having at least one memory device, or, on which at least one memory device is held or to which at least one memory device is mounted.

    APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES
    8.
    发明公开
    APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES 审中-公开
    设备和方法设置设备标识符SERIAL共享ASSOCIATES

    公开(公告)号：EP2021930A1

    公开(公告)日：2009-02-11

    申请号：EP07719813.3

    申请日：2007-05-18

    申请人： Mosaid Technologies Incorporated

    发明人： PYEON, Hong Beom ,  OH, HakJune ,  KIM, Jin-Ki

    IPC分类号： G06F13/00 ,  G06F13/42

    CPC分类号： G06F13/4256 ,  G06F2213/0052

    摘要： A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration.

    POWER SUPPLY TESTING ARCHITECTURE
    9.
    发明公开
    POWER SUPPLY TESTING ARCHITECTURE 审中-公开
    电源测试架构

    公开(公告)号：EP2005203A1

    公开(公告)日：2008-12-24

    申请号：EP07710714.2

    申请日：2007-03-08

    申请人： Mosaid Technologies Incorporated

    发明人： KIM, Jin-Ki

    IPC分类号： G01R31/40 ,  G06F1/28 ,  G11C16/00 ,  G11C29/00 ,  G11C5/14

    CPC分类号： G11C29/02 ,  G11C5/147 ,  G11C11/4074 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/2602

    摘要： A power supply testing architecture for embedded sub-systems is described, where each embedded sub-system can have at least one testable internal voltage supply. A plurality of embedded sub-systems are organized into groups, where each group of sub-systems shares a common voltage test line connected to the internal voltage supplies of the sub-systems. Accordingly, the collective internal voltages of each group can be tested in parallel. A power control signal can disable the internal voltage supply of all the sub-systems to allow application of an external power to the common voltage test lines. Alternately, the sub-systems in each group can be tested sequentially, such that each enabled sub-system of the group has dedicated access to its common voltage test line. In such a scheme, dedicated power control signals are used to independently disable each sub-system of the groups.