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公开(公告)号：EP3635924A1
公开(公告)日：2020-04-15
申请号：EP18729187.7
申请日：2018-05-11
IPC分类号： H04L25/02 , H03M1/12 , H03K17/689 , H03M3/00
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32.发明公开
公开(公告)号：EP3629480A2
公开(公告)日：2020-04-01
申请号：EP19195896.6
申请日：2019-09-06
发明人： SHABRA, Ayman , HO, Stacy , ASHBURN, Michael A
IPC分类号： H03M3/00
摘要： Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.
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公开(公告)号：EP3090536B1
公开(公告)日：2020-03-11
申请号：EP14814840.6
申请日：2014-12-16
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公开(公告)号：EP3618285A1
公开(公告)日：2020-03-04
申请号：EP19193421.5
申请日：2019-08-23
发明人： EGAN, Nathan
摘要： A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.
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公开(公告)号：EP3567722A1
公开(公告)日：2019-11-13
申请号：EP18171555.8
申请日：2018-05-09
申请人： ams AG
发明人： Auer, Mario , Karaca, Timucin
摘要： A Class-D amplifier for generating a driver signal from a multi-bit input signal comprises a digital pulse-width modulation, PWM, stage (DPWM) that is configured to generate a PWM signal (PWMA, PWMB) from the multi-bit input signal and a digital error feedback signal, and a power stage (PS) comprising a push-pull amplifier being controlled by the PWM signal (PWMA, PWMB) for generating the driver signal. A feedback stage (FB) generates the error feedback signal based on a difference between the driver signal and the PWM signal (PWMA, PWMB).
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36.发明公开
公开(公告)号：EP3565123A1
公开(公告)日：2019-11-06
申请号：EP18170512.0
申请日：2018-05-03
申请人： Intel IP Corporation
发明人： DI GIANDOMENICO, Antonio , PATON-ALVAREZ, Susana , FERNANDEZ-GUTIERREZ, Eric , HERNANDEZ-CORPORALES, Luis
摘要： A continuous time sigma delta modulator is provided. The modulator includes a ring oscillator configured to generate, based on an analog oscillator control signal, a plurality of phase shifted oscillation signals. Further, the modulator includes a plurality of sample circuits configured to generate a plurality of sampled signals by sampling each of the plurality of oscillation signals based on each of a plurality of phase shifted reference signals. The modulator additionally includes a digital-to-analog converter configured to generate an analog feedback signal based on the plurality of sampled signals. The oscillator control signal is based on the feedback signal.
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公开(公告)号：EP3502804A1
公开(公告)日：2019-06-26
申请号：EP18193113.0
申请日：2015-02-03
发明人： WU, Ying , STASZEWSKI, Robert , MAO, Yihong
摘要： A time-to-digital converter (300, 400) includes: an input (302, 402) for receiving a time-domain input signal (Tin); an output (306, 406) for providing a digital output signal (Dout); a time register (305, 405) coupled to the input (302, 403) and to a first node (308, 408); a time quantizer (307, 407) coupled to the time register (305, 405) for providing the digital output signal (Dout) at the output (306, 406); and a digital-to-time converter (309, 409) coupled to the output (306, 406) for providing a feed-back signal (E, Q err ) at the first node (308, 408).
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38.发明公开
公开(公告)号：EP3407498A1
公开(公告)日：2018-11-28
申请号：EP17172738.1
申请日：2017-05-24
申请人： ams AG
发明人： Horii, Daisuke
摘要： A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit (100) including a differential operational amplifier (130) having a first input node (E130a) and a second input node (E130b). A first current path (101) is coupled to a first reference input terminal (E100a) to apply a first reference potential (RefP) and the second current path (102) is coupled to a second reference input terminal (E100b) to apply a second reference potential (RefN). The at least one capacitor switch circuit (100) comprises a first controllable switch (111) being arranged between the second input node (E130a) of the differential operational amplifier (130) and the first current path (101). The at least one capacitor switch circuit (100) comprises a second controllable switch (112) being arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102).
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公开(公告)号：EP3255852B1
公开(公告)日：2018-11-28
申请号：EP16305675.7
申请日：2016-06-09
申请人： Alcatel Lucent
发明人： Markert, Daniel , Xin, Yu
CPC分类号： H04L25/4902 , H03M3/506
摘要： Examples relate to a concept generating at least one RF signal based on at least one digital baseband signal at a first clock rate. At least one digital pulse sequence at a second clock rate corresponding to a center frequency of the RF signal is modulated based on the digital baseband signal. Pulses of the pulse sequence are quantized based on a time grid of a third clock rate. A ratio between a number of second clock cycles corresponding to one first clock cycle and a number of third clock cycles corresponding to one first clock cycle is non-integer.
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公开(公告)号：EP3404836A1
公开(公告)日：2018-11-21
申请号：EP17171673.1
申请日：2017-05-18
发明人： GERFERS, Friedel , RUNGE, Marcel
IPC分类号： H03M3/00
摘要： An embodiment of the invention relates to a method of operating a system comprising a digital-to-analog-converter (18), wherein an output signal (yout(t), yout(n)) of the system is improved by completely or at least partly compensating a non-linearity error of the digital-to-analog-converter (18), said method comprising the steps of: determining an error value (X1, X2, X3, Xn, X 1,LH , X 1,ST , X 1,HL , X 2,LH , X 2,ST , X 2,HL , X N,LH , X N,ST , X N,HL ) that quantifies the deficiency of at least one weight (g1-gN) of the digital-to-analog-converter (18), determining a digital correction value (yc(n)) based on said error value, and completely or at least partly compensating the non-linearity error of the digital-to-analog-converter (18) on the basis of the digital correction value (yc(n)). The embodiment is further characterized in that a digital input signal (y(n)), that itself forms the input signal of the digital-to-analog-converter (18) or at least shows the same signal transitions (LH, ST, HL) over time as the input signal of the digital-to-analog-converter (18), is analyzed regarding a signal transition (LH, ST, HL) or signal transitions (LH, ST, HL) in the past. The step of determining the digital correction value (yc(n)) includes taking into account whether or not a signal transition (LH, ST, HL) or signal transitions (LH, ST, HL) have taken place in the past.
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