公开(公告)号：EP3353896A1

公开(公告)日：2018-08-01

申请号：EP16766119.8

申请日：2016-08-24

Applicant: Qualcomm Incorporated

Inventor： RAJAEE, Omid ,  HAN, Changsok ,  DAI, Liang ,  MIRHAJ, Seyed Arash ,  KIRAN, Ganesh

IPC: H03M3/00 ,  H03M1/46 ,  H03M1/10

CPC classification number: H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

Abstract: Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

公开(公告)号：EP3352376A1

公开(公告)日：2018-07-25

申请号：EP18152518.9

申请日：2018-01-19

Applicant: MediaTek Inc.

Inventor： HE, Tao ,  ASHBURN JR., Michael A.

IPC: H03M3/04

CPC classification number: H03M3/322 ,  H03M3/368 ,  H03M3/424 ,  H03M3/464

Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-Os and logic-Is occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-Os and logic-Is occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.

公开(公告)号：EP3350929A1

公开(公告)日：2018-07-25

申请号：EP16765946.5

申请日：2016-09-06

Applicant: Koninklijke Philips N.V.

Inventor： OUZOUNOV, Sotir Filipov ,  POL, Ketan

IPC: H03M3/00

CPC classification number: H03M3/49 ,  H03M3/32 ,  H03M3/322 ,  H03M3/422 ,  H03M3/43 ,  H03M3/438 ,  H03M3/464 ,  H03M3/496

Abstract: The invention describes a method of performing analog-to-digital conversion on an input signal (Pin) within a range (R1) using a sigma-delta modulator (1) comprising a feedback digital-to-analog conversion arrangement (12, 120), which method comprises the steps of: obtaining an amplitude estimate (E1, E2, E3, E4) of the input signal (Pin); defining a subsequent subrange (R2, R3, R4) on the basis of the amplitude estimate (E1, E2, E3); and adjusting operation parameters of the feedback digital-to-analog conversion arrangement (12, 120) on the basis of the subsequent subrange (R2, R3, R4); whereby the method steps are repeated a predefined number of iterations (N). The invention further describes a sigma-delta modulator (1), an analog-to-digital converter (50), and a monitoring device (5) for monitoring an analog input signal (Pin).

公开(公告)号：EP3340474A1

公开(公告)日：2018-06-27

申请号：EP16205911.7

申请日：2016-12-21

Applicant: Intel IP Corporation

Inventor： DI GIANDOMENICO, Antonio ,  KAMPUS, Vahur

IPC: H03M3/00 ,  H03M1/66

CPC classification number: H03M3/454 ,  H03M1/664 ,  H03M3/37 ,  H03M3/464 ,  H03M3/476

Abstract: Analog-to-digital converter devices and methods are provided, where feedback using a nonlinear digital-to-analog converter is used. In some implementations, such a nonlinear digital-to-analog converter feedback may be used to compensate extra loop delay while maintaining stability and/or not injecting any additional noise.

公开(公告)号：EP3236588A1

公开(公告)日：2017-10-25

申请号：EP16165986.7

申请日：2016-04-19

Applicant: ams AG

Inventor： Christen, Thomas ,  Steele, Colin ,  Fröhlich, Thomas

IPC: H03M3/04 ,  H03M1/12 ,  H03M1/68

CPC classification number: H03M3/49 ,  H03M1/1295 ,  H03M1/68 ,  H03M3/464

Abstract: A signal processing arrangement (100) has a signal input (SI) for connecting a capacitive sensor (CS). An amplifier circuit (AMP) is coupled between the signal input (SI) and a feedback point (CB1). A loop filter (LF) is coupled downstream to the feedback point (CB1). A quantizer (QT) is connected downstream to the loop filter (LF) and provides a multi-bit output word (OW). The multi-bit output word (OW) consists of one or more higher significance bits (HSB) and one or more lower significance bits (LSB). A first feedback path (FB1) is coupled between a quantizer (QT) and the feedback point (CB1) for providing a first feedback signal to the feedback point (CB1) being representative of the one or more lower significance bits (LSB). A second feedback path is coupled to the quantizer (QT) for providing a second feedback signal to the signal input (SI) being representative of the one or more higher significance bits (HSB).

Abstract translation: 信号处理装置（100）具有用于连接电容式传感器（CS）的信号输入（SI）。 放大器电路（AMP）耦合在信号输入端（SI）和反馈点（CB1）之间。 环路滤波器（LF）耦合到反馈点（CB1）的下游。 量化器（QT）连接到环路滤波器（LF）的下游并提供多位输出字（OW）。 多位输出字（OW）由一个或多个较高有效位（HSB）和一个或多个较低有效位（LSB）组成。 第一反馈路径（FB1）耦合在量化器（QT）与反馈点（CB1）之间，用于向表示一个或多个较低有效位（LSB）的反馈点（CB1）提供第一反馈信号。 第二反馈路径耦合到量化器（QT），用于向表示一个或多个较高有效位（HSB）的信号输入（SI）提供第二反馈信号。

公开(公告)号：EP2936688B1

公开(公告)日：2017-05-03

申请号：EP12809825

申请日：2012-12-21

Applicant: TELEDYNE DALSA B V

Inventor： SCHINKEL DANIEL ,  GROOTHEDDE WOUTER

IPC: H03M3/02

CPC classification number: H03M3/464 ,  H03F3/181 ,  H03F3/45 ,  H03F2200/03 ,  H03F2200/331 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03M3/43 ,  H03M3/438 ,  H03M3/446

公开(公告)号：EP2809007B1

公开(公告)日：2017-03-22

申请号：EP14168345.8

申请日：2014-05-14

Applicant: Analog Devices Global

Inventor： Caldwell, Trevor Clifford ,  Schreier, Richard E. ,  Alldred, David ,  Yang, Wenhua W.

IPC: H03M1/06 ,  H03M1/36 ,  H03M1/74 ,  H03M3/00

CPC classification number: H03M1/0673 ,  H03M1/361 ,  H03M1/74 ,  H03M3/30 ,  H03M3/338 ,  H03M3/464

公开(公告)号：EP2913929A2

公开(公告)日：2015-09-02

申请号：EP15156825.0

申请日：2015-02-26

Applicant: Analog Devices Global

Inventor： Dong, Yunzhi ,  Li, Zhao ,  Schreier, Richard E. ,  Shibata, Hajime ,  Caldwell, Trevor Clifford

IPC: H03M1/14

CPC classification number: H03K5/159 ,  H03M1/0626 ,  H03M1/14 ,  H03M1/145 ,  H03M1/38 ,  H03M3/414 ,  H03M3/464

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格的延迟元件来实现高性能CT流水线ADC和CT delta-sigma（“£”）ADC。 使用基于LC晶格的延迟元件为具有良好控制阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路部分，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

公开(公告)号：EP2840715A1

公开(公告)日：2015-02-25

申请号：EP12874532.0

申请日：2012-04-19

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： WATANABE, Hikaru

IPC: H03M3/02

CPC classification number: H03M3/422 ,  H03M3/374 ,  H03M3/39 ,  H03M3/416 ,  H03M3/424 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464

Abstract: The present invention relates to a delta-sigma-modulator and a delta-sigma-A/D converter. By speeding up the settling time constant of an integrator at the last stage with a simple configuration, the sampling frequency is sped up in the delta-sigma-modulator as a whole. Specifically, in the delta-sigma-modulator including multiple integrators connected in cascade, the integrator positioned at the last stage is a passive integrator not using an amplifier circuit, and one or more integrators positioned at stages preceding the last stage by one or more stages are active SC integrators using amplifier circuits and switched capacitor circuits, respectively. Also, each of the integrators performs integral calculation by alternately repeating a first operation phase to charge a sampling capacitor by sampling an input signal, and a second operation phase to perform a summing integration by transferring an electric charge charged in the sampling capacitor to an integration capacitor.

Abstract translation: 本发明涉及Δ-Σ调制器和Δ-Σ-A / D转换器。 通过以简单的配置，在最后阶段加速积分器的稳定时间常数，采样频率在整个Δ-Σ调制器中加快。 具体地说，在包括串联连接的多个积分器的Δ-Σ调制器中，位于最后级的积分器是不使用放大器电路的无源积分器，以及一个或多个积分器，其位于最后一级之前的一级或多级 是分别使用放大器电路和开关电容电路的有源SC积分器。 此外，每个积分器通过交替地重复第一操作阶段来对第一操作阶段进行积分计算，以通过对输入信号进行采样来对采样电容器进行充电;以及第二操作阶段，以通过将在采样电容器中充电的电荷转移到积分来执行求和积分 电容。

公开(公告)号：EP2592756A1

公开(公告)日：2013-05-15

申请号：EP11189057.0

申请日：2011-11-14

Applicant: Telefonaktiebolaget L M Ericsson AB (Publ)

Inventor： Anderson, Martin ,  Sundström, Lars

IPC: H03M3/02

CPC classification number: H03M3/396 ,  H03M3/374 ,  H03M3/436 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464 ,  H04B1/16 ,  H04W88/02 ,  H04W88/08

Abstract: A continuous-time ΣΔ-ADC (1) is disclosed. It comprises a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ΔΣ-ADC (1) at sample instants nT, where n is an integer sequence index and T is a sampling period, based on an analog input signal to the quantizer (5). Furthermore, the ΔΣ-ADC (1) comprises one or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5). Moreover, the ΔΣ-ADC (1) comprises a continuous-time analog network (20) arranged to generate the analog input signal to the quantizer (5) based on the feedback signal(s) from the one or more DACs (10a-b) and an analog input signal to the ΔΣ-ADC (1). At least one DAC (10b) of the one or more DACs (10b) comprises two switched-capacitor DACs (40, 50) arranged to operate on the same input but with a mutual delay in time. A corresponding radio receiver circuit (100), a corresponding integrated circuit (200), and a corresponding radio communication apparatus (300, 400) are also disclosed.

Abstract translation: 公开了连续时间“-ADC（1）”。 它包括一个采样量化器（5），被配置为产生在样本时刻nT处的“-ADC（1）”的数字输出信号的样本y（n），其中n是整数序列索引，T是采样周期 对量化器（5）的模拟输入信号。 此外，“-ADC（1）”包括一个或多个DAC（10a-b），每个DAC（10a-b）被布置为基于由采样的量化器（5）生成的数字输出信号的采样来产生模拟反馈信号。 此外，“-ADC（1）包括连续时间模拟网络（20），其被布置为基于来自所述一个或多个DAC（10a-）的反馈信号来产生到量化器（5）的模拟输入信号， b）和到“£-ADC（1）”的模拟输入信号。 一个或多个DAC（10b）的至少一个DAC（10b）包括布置成在相同输入上操作但具有相互延迟的两个开关电容器DAC（40,50）。 还公开了相应的无线电接收器电路（100），相应的集成电路（200）和相应的无线电通信装置（300,400）。