公开(公告)号：EP3642959B1

公开(公告)日：2023-11-08

申请号：EP18821224.5

申请日：2018-06-19

发明人： SETE, Eyob A. ,  DIDIER, Nicolas ,  DA SILVA, Marcus Palmer ,  RIGETTI, Chad Tyler ,  REAGOR, Matthew J. ,  CALDWELL, Shane Arthur ,  TEZAK, Nikolas Anton ,  RYAN, Colm Andrew ,  HONG, Sabrina Sae Byul ,  SIVARAJAH, Prasahnt ,  PAPAGEORGE, Alexander ,  ABRAMS, Deanna Margo

IPC分类号： H03K19/195 ,  G06N99/00 ,  B82Y10/00

公开(公告)号：EP4261893A1

公开(公告)日：2023-10-18

申请号：EP23155297.7

申请日：2023-02-07

申请人： Samsung Electronics Co., Ltd.

发明人： BAEK, Bong Kwan ,  LIM, Jun Hyuk ,  CHUN, Jung Hwan ,  HAN, Kyu-Hee ,  BAEK, Jong Min ,  RYU, Koung Min ,  SHIN, Jung Hoo ,  JANG, Sang Shin

IPC分类号： H01L29/06 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/336 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00

摘要： Semiconductor devices with improved performance and reliability and methods for forming the same are provided. The semiconductor devices include an active pattern (AP1) extending in a first direction (X), gate structures (GS) spaced apart from each other in the first direction on the active pattern (AP1), a source/drain pattern (150) on the active pattern (AP1), a source/drain contact (170) on the source/drain pattern (150), and a contact liner (175) extending along a sidewall (170_SW) of the source/drain contact (170). A carbon concentration of the contact liner (175) at a first point (PS1) of the contact liner (175) is different from a carbon concentration of the contact liner (175) at a second point (PS2) of the contact liner (175), and the first point (PS1) is at a first height from an upper surface (AP1_US) of the active pattern (AP1), the second point (PS2) is at a second height from the upper surface (AP1_US) of the active pattern (AP1), and the first height is smaller than the second height.

公开(公告)号：EP4260250A1

公开(公告)日：2023-10-18

申请号：EP21904328.8

申请日：2021-12-08

申请人： Mastercard International Incorporated

发明人： MARIELLA, Nicola ,  FLINTER, Stephen, Patrick

IPC分类号： G06N10/80 ,  G06N10/60 ,  B82Y10/00

公开(公告)号：EP4252160A2

公开(公告)日：2023-10-04

申请号：EP21911850.2

申请日：2021-11-19

申请人： Psiquantum Corp.

发明人： SMITH, Jake ,  KEILING, Konrad

IPC分类号： G06N10/40 ,  B82Y10/00

公开(公告)号：EP4252157A1

公开(公告)日：2023-10-04

申请号：EP21785860.4

申请日：2021-09-28

申请人： IST Austria - Institute of Science and Technology Austria

发明人： KATSAROS, Georgios ,  JIROVEC, Daniel

IPC分类号： G06N10/00 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/66

公开(公告)号：EP4246590A2

公开(公告)日：2023-09-20

申请号：EP23161820.8

申请日：2023-03-14

申请人： Silicon Quantum Computing Pty Ltd

发明人： KRANZ, Ludwik ,  SIMMONS, Michelle Yvonne ,  RAHMAN, Rajib

IPC分类号： H01L29/12 ,  H01L29/36 ,  H01L29/423 ,  H01L29/76 ,  B82Y10/00

摘要： A quantum processing element is disclosed. The qubit includes a semiconductor substrate (204), a dielectric material (205) forming an interface with the semiconductor substrate, a confinement gate (211) and antenna (214) on the dielectric material, and a donor molecule (208a, 208b) embedded in the semiconductor. The donor molecule includes a plurality of dopant dots (210a, 210b, 210c) embedded in the semiconductor, each dopant dot includes one or more dopant atoms, and one or more electrons/holes confined to the dopant dots. A distance between the dopant dots is between 3 and 9 nanometres.

公开(公告)号：EP3394898B1

公开(公告)日：2023-09-20

申请号：EP15911549.2

申请日：2015-12-24

发明人： JAMBUNATHAN, Karthik ,  GLASS, Glenn ,  MURTHY, Anand ,  KANG, Jun Sung ,  KIM, Seiyon

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/775

公开(公告)号：EP4235801A2

公开(公告)日：2023-08-30

申请号：EP23167162.9

申请日：2011-11-23

申请人： Sony Group Corporation

发明人： KUHN, Kelin J. ,  KIM, Seiyon ,  RIOS, Rafael ,  CEA, Stephen M. ,  GILES, Martin D. ,  CAPPELLANI, Annalisa ,  RAKSHIT, Titash ,  CHANG, Peter ,  RACHMADY, Willy

IPC分类号： H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L21/336 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：EP4022682B1

公开(公告)日：2023-07-26

申请号：EP20804521.1

申请日：2020-11-10

发明人： HOLMES, Steven ,  SADANA, Devendra ,  HART, Sean ,  LI, Ning ,  BEDELL, Stephen ,  GUMANN, Patryk

IPC分类号： H10N69/00 ,  B82Y10/00 ,  G06N10/00 ,  H10N60/10 ,  H10N60/01

公开(公告)号：EP4203057A1

公开(公告)日：2023-06-28

申请号：EP22201131.4

申请日：2022-10-12

申请人： INTEL Corporation

发明人： HASAN, Mohammad ,  KUMAR, Nitesh ,  SHAH, Rushabh ,  MURTHY, Anand S. ,  PATEL, Pratik ,  GHANI, Tahir ,  MEYER, Tricia ,  BOMBERGER, Cory ,  GLASS, Glenn A. ,  CEA, Stephen M. ,  JAHAGIRDAR, Anant H.

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/10

摘要： Gate-all-around integrated circuit structures having source or drain structures (124) with substrate connection portions (124A), and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires (108). A gate stack (126, 128) is over the vertical arrangements of nanowires (108) and completely surrounding each nanowire (108). A first epitaxial source or drain structure (124) is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure (124) is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion (124B) and a lower epitaxial extension portion (124A), the latter being recessed into the substrate (102).