SEMICONDUCTOR DEVICE QFN PACKAGE AND METHOD OF MAKING THEREOF

    公开(公告)号:EP4163967A1

    公开(公告)日:2023-04-12

    申请号:EP22197358.9

    申请日:2022-09-23

    申请人: NXP USA, Inc.

    IPC分类号: H01L23/495 H01L23/31

    摘要: The present invention relates to a quad-flat-no-leads (QFN) packaged semiconductor device having a QFN bottom surface and QFN side faces, wherein the QFN side faces each comprise an upper portion and a recessed lower portion, the QFN packaged semiconductor device comprising: a die pad within or on the QFN bottom surface; a plurality of I/O terminals spaced apart from the die pad and around a periphery of the bottom surface, each having a bottom face extending from an inner end to a peripheral end, an exposed side face on a QFN side face and extending above the recessed lower portion of the QFN side face; wherein the QFN bottom surface includes at least one trench therein, parallel to a one of the QFN side faces and exposing at least a part of a side face of the inner end of the I/O terminals. The trench may provide for additional surface area, and provide a stronger solder joint when the QFN packaged semiconductor device is soldered to a substrate or circuit board.

    WIRE BONDED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:EP4163966A1

    公开(公告)日:2023-04-12

    申请号:EP22198870.2

    申请日:2022-09-29

    申请人: NXP USA, Inc.

    IPC分类号: H01L23/49 H01L23/31 H01L21/60

    摘要: A method of packaging a semiconductor device includes: bonding a ball (304) at an end of a bond wire (302) to a bond pad (204) of a semiconductor device die (200) in an aperture of a shielding layer (206) of the semiconductor device; and sealing the part of the bond pad (204) exposed by the aperture of the shielding layer (206) by deforming the ball (304) of the bond wire (302) to fill the aperture of the shielding layer (206). The aperture of the shielding layer (206) includes an edge wall, and exposes a part of the bond pad (204). The shielding layer (206) covers a remaining part of the bond pad (204). The aperture of the shielding layer (206) is completely filled with the ball (304) of the bond wire (302), thereby deforming the edge wall of the shielding layer (206).

    CONTROLLER AREA NETWORK TRANSCEIVER
    44.
    发明公开

    公开(公告)号:EP4152700A1

    公开(公告)日:2023-03-22

    申请号:EP22190438.6

    申请日:2022-08-15

    申请人: NXP B.V.

    IPC分类号: H04L12/40

    摘要: A Controller Area Network (CAN) transceiver includes a receiver configured to determine a voltage differential signal from analog signalling received from a CAN bus and configured to provide a digital output signal at a receiver output to a CAN controller based on the voltage differential signal. The receiver includes arming circuitry configured to place the receiver in an armed or unarmed state based on the voltage differential signal, a first threshold corresponding to a first CAN protocol, and a second threshold corresponding to a second CAN protocol. When the receiver is in the unarmed state, a first digital signal indicative of activity on the CAN bus is provided based on a comparison between the voltage differential signal and the first threshold, and when in the armed state, the first digital signal is provided based on comparisons between the voltage differential signal and each of the first and the second thresholds.

    PRIORITY QUEUE SORTING SYSTEM AND METHOD WITH DETERMINISTIC AND BOUNDED LATENCY

    公开(公告)号:EP4123992A1

    公开(公告)日:2023-01-25

    申请号:EP22185000.1

    申请日:2022-07-14

    申请人: NXP B.V.

    摘要: A priority queue sorting system including a priority queue and a message storage. The priority queue includes multiple priority blocks that are cascaded in order from a lowest priority block to a highest priority block. Each priority block includes a register block storing an address and an identifier, compare circuitry that compares a new identifier with the stored identifier for determining relative priority, and select circuitry that determines whether to keep or shift and replace the stored address and identifier within the priority queue based on the relative priority. The message storage stores message payloads, each pointed to by a corresponding stored address of a corresponding priority block. Each priority block contains its own compare and select circuitry and determines a keep, shift, or store operation. Thus, sorting is independent of the length of the priority queue thereby achieving deterministic sorting latency that is independent of the queue length.

    SEMICONDUCTOR DEVICE PACKAGING WARPAGE CONTROL

    公开(公告)号:EP4099367A3

    公开(公告)日:2022-12-28

    申请号:EP22175069.8

    申请日:2022-05-24

    申请人: NXP USA, Inc.

    摘要: A method of manufacturing a packaged semiconductor device is provided. The method includes placing a plurality of semiconductor die on a carrier substrate. The plurality of semiconductor die and an exposed portion of the carrier substrate are encapsulated with an encapsulant. A cooling fixture includes a plurality of nozzles and is placed over the encapsulant. The encapsulant is cooled by way of air exiting the plurality of nozzles. A property of air exiting a first nozzle of the plurality of nozzles is different from that of a second nozzle of the plurality of nozzles.