公开(公告)号：EP2551776A4

公开(公告)日：2015-09-02

申请号：EP10848404

申请日：2010-03-25

Applicant: FUJITSU LTD

Inventor： YAMAUCHI HIROMASA ,  YAMASHITA KOICHIRO ,  MIYAZAKI KIYOSHI ,  IKEDA HITOSHI

IPC: G06F13/18 ,  G06F9/50 ,  G06F12/00 ,  G06F13/362 ,  G06F15/167

CPC classification number: G06F9/5027 ,  G06F13/1605 ,  G06F13/362 ,  G06F13/3625 ,  G06F2209/5021

Abstract: When process A-1-1 is assigned to CPU#0 and CPU#1, a scheduler (111) obtains the priority of process A-1-1 and the number of accesses by each of process assigned to CPUs. The scheduler (111) determines whether the priority of process A-1-1 is high. The priority of process A-1-1 is high since process A-1-1 is a doacross process that has a dependency between iterations and thus accesses a bus frequently. If the scheduler (111) determines the priority of process A-1-1 is high, the scheduler (111) determines an access ratio based on the obtained number of accesses, and notifies an arbitration circuit (102) of the access ratio. The arbitration circuit (102) arbitrates accesses from CPU#0 to CPU#7 according to weighted round robin based on the notified access ratio.

公开(公告)号：EP2856690A1

公开(公告)日：2015-04-08

申请号：EP13796542.2

申请日：2013-03-14

Applicant: BlackBerry Limited

Inventor： POULSEN, Jens Kristian

IPC: H04L7/00 ,  H04L1/24

CPC classification number: G06F13/3625 ,  G06F1/12 ,  H04J3/06 ,  H04L1/1607 ,  H04L7/041 ,  H04L7/042 ,  H04L7/048 ,  H04L7/10 ,  H04L2001/0094

Abstract: Various embodiments are described herein related to techniques for synchronizing a slave device to a master device that communicates using a unified bus communication protocol or some aspect thereof. In one example, the method may comprise assuming a first mode of operation for the unified bus communication protocol; searching for a synchronization pattern at one or more locations in transmitted data according to the first mode of operation; obtaining synchronization when the located synchronization pattern is verified according to at least one synchronization rule for the mode of operation; and if synchronization is not obtained based on the assumed first mode of operation, a second mode of operation for the unified bus communication protocol is assumed and the searching and obtaining acts are carried out on the transmitted data according to the second mode of operation.

公开(公告)号：EP2551776A1

公开(公告)日：2013-01-30

申请号：EP10848404.9

申请日：2010-03-25

Applicant: Fujitsu Limited

Inventor： YAMAUCHI, Hiromasa ,  YAMASHITA, Koichiro ,  MIYAZAKI, Kiyoshi ,  IKEDA, Hitoshi

IPC: G06F13/18 ,  G06F12/00

CPC classification number: G06F9/5027 ,  G06F13/1605 ,  G06F13/362 ,  G06F13/3625 ,  G06F2209/5021

Abstract: When process A-1-1 is assigned to CPU#0 and CPU#1, a scheduler (111) obtains the priority of process A-1-1 and the number of accesses by each of process assigned to CPUs. The scheduler (111) determines whether the priority of process A-1-1 is high. The priority of process A-1-1 is high since process A-1-1 is a doacross process that has a dependency between iterations and thus accesses a bus frequently. If the scheduler (111) determines the priority of process A-1-1 is high, the scheduler (111) determines an access ratio based on the obtained number of accesses, and notifies an arbitration circuit (102) of the access ratio. The arbitration circuit (102) arbitrates accesses from CPU#0 to CPU#7 according to weighted round robin based on the notified access ratio.

Abstract translation: 当进程A-1-1被分配给CPU＃0和CPU＃1时，调度器（111）获得进程A-1-1的优先级以及分配给CPU的每个进程的访问次数。 调度器（111）确定进程A-1-1的优先级是否高。 进程A-1-1的优先级很高，因为进程A-1-1是一个doacross进程，它在迭代之间具有相关性，因此频繁访问总线。 如果调度器（111）确定进程A-1-1的优先级为高，则调度器（111）基于获得的访问次数来确定访问比率，并且向仲裁电路（102）通知访问比率。 仲裁电路（102）基于所通知的访问比率，根据加权循环法来仲裁从CPU＃0到CPU＃7的访问。

公开(公告)号：EP2423824A1

公开(公告)日：2012-02-29

申请号：EP11177989.8

申请日：2011-08-18

Applicant: Ricoh Company, Ltd.

Inventor： Sasaki, Fumihiro

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F13/3625

Abstract: A data transfer device (222) controls data transfer performed through a bus (223) capable of separately processing a request and a response. The data transfer device include a plurality of access control units (230a-230d) that produce a data transfer process according to the request; and an arbitration unit (231) that performs arbitration between the requests issued by the plurality of access control units so as to determine a request to be accepted among those requests. The arbitration unit sets an arbitration prohibited period in which the arbitration is prohibited for a designated period and accepts only the request issued by a designated access control unit (230a) among the plurality of access control units during the arbitration prohibited period.

Abstract translation: 一种数据传送装置（222）控制能够单独地处理请求和响应通过总线（223）上进行数据传输。 数据传送装置包括的访问控制单元（230A-230D）确实产生的数据传输处理gemäß到请求多个; 和仲裁单元（231）没有通过的访问控制单元的多元发出以便确定性矿请求以这些请求中被接受的请求之间进行仲裁。 仲裁单元集来仲裁禁止时段，其中所述仲裁被禁止一段指定的时期和只接受在仲裁期间禁止通过的访问控制单元的多元性中的指定访问控制单元（230）发出的请求。

公开(公告)号：EP1187032B1

公开(公告)日：2012-01-04

申请号：EP01000442.2

申请日：2001-09-10

Applicant: TEXAS INSTRUMENTS INC.

Inventor： Jahnke, Steven R. ,  Hamakawa, Hiromichi

IPC: G06F13/40

CPC classification number: G06F13/24 ,  G06F13/3625 ,  G06F13/4031

公开(公告)号：EP1939755A3

公开(公告)日：2008-07-30

申请号：EP07123186.4

申请日：1995-07-31

Applicant: FUJITSU LIMITED

Inventor： Koyama, Susumu c/o FUJITSU LIMITED

IPC: G06F13/362 ,  G06F3/06

CPC classification number: G06F13/24 ,  G06F3/0601 ,  G06F13/126 ,  G06F13/3625 ,  G06F2003/0698

Abstract: An apparatus for processing an input/output request from a set of upper units 14-i using a plurality of channel buses 18-i of different transfer speeds, comprising: a plurality of input/output ports 20-i connected to a plurality of channel units on the upper unit side through the plurality of channel buses; a route-control section 46 for executing a coupling in association with an activation request from the channel unit for one of the input/output ports, a transfer process during the coupling, a response of an end status in association with the end of transfer, and a busy response for the activation request during the coupling of the other input/output port; and a retry interrupt processing section 76 for processing in a manner such that in the case where a predetermined interrupt condition is satisfied during the transfer process by the coupling between a specific channel unit and the input/output port by the route-control section, a retry status is transmitted from the input/output port to the channel unit, the transfer process is interrupted, the coupling is disconnected, states of the busy responses regarding all of the ports are analyzed, a preferential processing port is decided, an end status is transmitted from this preferential processing port to its channel unit in order to allow this other channel to execute the activation request, and at the time of the end of the transfer process in association with the activation request an interruption of a retry start is notified to the said channel unit from the input/output port, thereby restarting the interrupted transfer process.

公开(公告)号：EP1668457A4

公开(公告)日：2008-01-23

申请号：EP04784429

申请日：2004-09-16

Applicant: TELLABS PETALUMA INC

Inventor： RIPY PAUL B ,  CHUNG KEITH Q ,  GEERDES GARY J ,  LEROY CHRISTOPHE P

IPC: G06F13/14 ,  G06F20060101 ,  G06F12/00 ,  G06F13/362

CPC classification number: G06F13/3625

Abstract: Access to a bus (110) is granted to one of a number of requesting communication circuits (116) that each submitted a bus control request during a request period of an arbitration period in response to the entries stored in a priority table in a memory (510). If a requesting communication circuit (116) has an identity and priority that match the identity and priority of a communication circuit (116) stored in a row of the priority table in the memory (510) that corresponds with the arbitration period, access to the bus (110) is granted to the requesting communication circuit (116).

公开(公告)号：EP1704487B1

公开(公告)日：2007-09-19

申请号：EP05797447.9

申请日：2005-07-28

Applicant: Sony Computer Entertainment Inc. ,  International Business Machines Corporation

Inventor： KING, Matthew, Edward ,  LIU, Peichun, Peter ,  MUI, David ,  YAMAZAKI, Takeshi

IPC: G06F13/28 ,  G06F13/362

CPC classification number: G06F13/28 ,  G06F13/3625

Abstract: An apparatus, a method and a computer program are provided for executing Direct Memory Access (DMA) commands. A physical queue is divided into a number of virtual queues by software based on the command type, such as processor to processor, processor to Input/Output (I/0) devices, and processor to external or system memory. Commands are then assigned to a slot based on the type of DMA command: load or store. Once assigned, the commands can be executed by alternating between the slots and by utilizing round robin systems within the slots in order to provide a more efficient manner to execute DMA commands.

公开(公告)号：EP1668457A2

公开(公告)日：2006-06-14

申请号：EP04784429.5

申请日：2004-09-16

Applicant: Tellabs Petaluma, Inc.

Inventor： RIPY, Paul, B. ,  CHUNG, Keith, Q. ,  GEERDES, Gary, J. ,  LEROY, Christophe, P.

IPC: G06F1/00

CPC classification number: G06F13/3625

Abstract: Access to a bus (110) is granted to one of a number of requesting communication circuits (116) that each submitted a bus control request during a request period of an arbitration period in response to the entries stored in a priority table in a memory (510). If a requesting communication circuit (116) has an identity and priority that match the identity and priority of a communication circuit (116) stored in a row of the priority table in the memory (510) that corresponds with the arbitration period, access to the bus (110) is granted to the requesting communication circuit (116).

公开(公告)号：EP0703535B1

公开(公告)日：2002-01-23

申请号：EP95305348.5

申请日：1995-07-31

Applicant: FUJITSU LIMITED

Inventor： Koyama, Susumu, c/o Fujitsu Limited

IPC: G06F13/362 ,  G06F3/06

CPC classification number: G06F13/24 ,  G06F3/0601 ,  G06F13/126 ,  G06F13/3625 ,  G06F2003/0698