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41.发明公开
公开(公告)号：EP0911726A2
公开(公告)日：1999-04-28
申请号：EP98307742.1
申请日：1998-09-24
发明人： Bak, Lars , Greisemer, Robert , Holzle, Urs
CPC分类号： G06F9/461 , G06F9/4484 , G06F9/45504
摘要： Systems and methods for implementing an execution stack which stores frames for functions written in multiple programming languages are provided. The frames for functions written in different programming languages may be interleaved on the same execution stack. A data block on the execution stack may be utilized to traverse the execution stack around a frame by storing a stack pointer and frame pointer to a previous frame. Additionally, exceptions may be propagated, with conversion if necessary, through frames on the execution stack that are written in different programming languages.
摘要翻译： 提供了用于实现用于存储以多种编程语言编写的功能的帧的执行堆栈的系统和方法。 以不同编程语言编写的函数的帧可以在相同的执行堆栈上进行交织。 可以利用执行堆栈上的数据块通过将堆栈指针和帧指针存储到先前帧来遍历帧周围的执行堆栈。 另外，异常可以传播，如果需要，通过转换，通过使用不同编程语言编写的执行堆栈上的帧。
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公开(公告)号：EP0897147A2
公开(公告)日：1999-02-17
申请号：EP98304702.8
申请日：1998-06-15
CPC分类号： G06F9/324 , G06F9/30101 , G06F9/30167 , G06F9/322 , G06F9/3885 , G06F9/461
摘要： A processor includes a constant register 36 for storing a constant, a format decoder 21 for decoding a format code located in the P0.0 field of an instruction stored in the instruction register 10, and a constant register control unit 32 which, when the format decoder 21 has decoded that the instruction includes a constant to be stored in the constant register 36, shifts the presently stored value in the constant register 36 and stores the constant into the constant register 36.
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公开(公告)号：EP0766170A1
公开(公告)日：1997-04-02
申请号：EP96202727.2
申请日：1996-09-30
CPC分类号： G06F9/4843 , G06F9/44521 , G06F9/44563 , G06F9/461
摘要： A method for providing per-instance data memory in a particular dynamic link library loaded in a random access memory address space both as part of a first task and as part of a second task loaded in the address space simultaneously, in a computer having memory management hardware including a local descriptor table to map selectors to base addresses. The method includes providing a task switch enhancer DLL (the TSE); providing in the TSE a DLL registration routine to register a DLL with the TSE; providing in the particular DLL a call to the DLL registration routine; providing in the TSE a task registration routine to register a task with the TSE; providing in the first task and in the second task a call to the task registration routine; providing a routine requesting the operating system to provide a switching notification whenever execution of any task is about to begin or end and whenever any task is about to cease to exist; providing in the TSE a segment allocation routine for allocating a memory segment for storing per-instance data of a DLL for a task as a substitute for an original per-instance data segment for that task, and maintaining a substitute base address being a base address for the allocated segment in the LDT entry and maintaining an original base address being the original base address of the original segment in the LDT entry; calling the TSE segment allocation routine for a per-instance data segment of the particular DLL for the first task during initialization of the first task and calling the TSE segment allocation routine for a per-instance data segment of the particular DLL for the second task during initialization of the second task; providing in the TSE a base address setup routine to store in the LDT entry the substitute base address of a per-instance segment of a task before that task begins execution; and invoking the base address setup routine for the substitute base address for the first task in response to a switching notification received by the TSE that the first task is about to begin execution.
摘要翻译： 一种在具有存储器管理的计算机中，将加载在随机存取存储器地址空间中的特定动态链接库中的每个实例数据存储器作为第一任务的一部分提供并且作为在地址空间中同时加载的第二任务的一部分的方法 硬件包括一个本地描述符表，用于将选择器映射到基地址。 该方法包括提供任务切换增强器DLL（TSE）; 在TSE中提供DLL注册程序以向TSE注册DLL; 在特定DLL中提供对DLL注册例程的调用; 在TSE中提供一个任务注册程序，以便向TSE注册任务; 在第一任务和第二任务中提供对任务登记例程的调用; 提供一个例程，要求操作系统在任何执行任务即将开始或结束以及任何任务即将停止存在时提供切换通知; 在TSE中提供段分配例程，用于分配用于存储用于任务的DLL的每个实例数据的存储器段作为用于该任务的原始每个实例数据段的替代，并且保持替代基地址作为基地址 对于LDT条目中的分配段，并维持原始基地址作为LDT条目中原始段的原始基地址; 在第一任务的初始化期间为第一任务的特定DLL的每个实例数据段调用TSE段分配例程，并为第二个任务的特定DLL的每个实例数据段调用TSE段分配例程 第二任务的初始化; 在TSE中提供基地址设置例程，以在该任务开始执行之前将任务的每个实例段的替代基地址存储在LDT条目中; 以及响应于由TSE接收到的第一个任务即将开始执行的切换通知，为第一个任务的替代基地址调用基地址设置例程。
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公开(公告)号：EP0760137A1
公开(公告)日：1997-03-05
申请号：EP95918962.0
申请日：1995-05-12
CPC分类号： G06F9/4812 , G06F9/461 , G06F15/17
摘要： In a parallel processing computer (100) containing a plurality of processors (106n, 108n, 110n), each connected to a memory unit (112n, 114n, 116n), a method and apparatus for accessing a distributed data buffer. Each of the processors within the computer executes a first routine for processing input data to generate output data. During processing, some or all of the data associated with the processing is temporarily stored within a predefined portion of each of the memory units that form a portion of the distributed data buffer. Upon occurrence of an interrupt signal, execution of the first routine is halted. Also, the status of the computer at the time the interrupt signal occured is stored in memory. Thereafter, a second routine (an interrupt routine) is executed to access the data stored in the data buffer. Once the data is accessed, the status of the computer is restored in accordance with the previously stored computer status information. Lastly, the first stored routine is restarted at a position therein at which the first routine was interrupted to execute the second routine.
摘要翻译： 在包含多个处理器（106n，108n，110n）的并行处理计算机（100）中，每个处理器都连接到存储器单元（112n，114n，116n），用于访问分布式数据缓冲器的方法和设备。 计算机内的每个处理器执行用于处理输入数据以产生输出数据的第一例程。 在处理期间，与处理相关联的一些或全部数据被暂时存储在形成分布式数据缓冲器的一部分的每个存储器单元的预定义部分内。 在发生中断信号时，停止执行第一例程。 另外，中断信号发生时计算机的状态存储在内存中。 此后，执行第二例程（中断例程）以访问存储在数据缓冲器中的数据。 一旦数据被访问，计算机的状态将按照先前存储的计算机状态信息被恢复。 最后，第一存储例程在其中第一例程被中断的位置重新开始以执行第二例程。
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公开(公告)号：EP0142982B1
公开(公告)日：1991-12-04
申请号：EP84307874.2
申请日：1984-11-14
发明人： Zardiackas, Fredrick
IPC分类号： G06F9/46
CPC分类号： G06F9/4812 , G06F9/461
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公开(公告)号：EP0282213A3
公开(公告)日：1991-04-24
申请号：EP88301751.9
申请日：1988-03-01
申请人： AT&T Corp.
CPC分类号： G06F9/544 , G06F9/461 , G06F9/468 , G06F12/1036
摘要： There is disclosed a memory management arrangement which facilitates interprocess data transfers by eliminating the need to construct temporary mapping tables when performing the data transfer operation. The arrangement includes the use of multiple and concurrent mapping tables in conjunction with the transmission of mapping table identification bits with each data transfer operation.
摘要翻译： 公开了一种存储器管理装置，其通过在执行数据传送操作时消除构建临时映射表的需要来促进进程间数据传输。 该布置包括使用多个并发映射表与每个数据传送操作的映射表识别位的传输相结合。
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公开(公告)号：EP0211152A3
公开(公告)日：1989-07-26
申请号：EP86105950.9
申请日：1986-04-30
IPC分类号： G06F15/347
CPC分类号： G06F9/3887 , G06F9/30036 , G06F9/30105 , G06F9/30112 , G06F9/3013 , G06F9/3885 , G06F9/461 , G06F15/8076
摘要： The invention relates to vector registers (VRs) which have associated therewith a vector status register (VSR) that includes VR status information in the form of vector in-use and change bits for saving and restoring (the contents of) the VRs. When the vector in-use bit for a VR is zero, the saving and subsequent restoring of the VR is eliminated because the VR is known to contain all zeros. This reduces program switching time. The vector change bit for a VR serves to reduce switching time still further by permitting the saving of a VR to be eliminated when its vector in-use bit is one but the vector change bit is zero. Although such a VR is in use, its content has not been changed since the last restore from the same save area in storage. The previously saved information is still valid. The vector change bits do not affect the restoring of vector registers and, therefore, do not reduce the restore time.
摘要翻译： 本发明涉及与矢量寄存器（VR）相关联的向量状态寄存器（VSR），该向量状态寄存器包括以向量使用的形式的VR状态信息和用于保存和恢复VR的内容的改变位。 当VR的向量使用位为零时，VR的保存和随后的恢复被消除，因为已知VR包含全部零。 这减少了程序切换时间。 用于VR的矢量改变位用于通过允许当其矢量使用位为1而矢量改变位为零时允许保存VR被消除而进一步减少切换时间。 虽然这样的VR正在使用，但是自从上一次从存储区域的存储区域恢复之后，其内容没有被改变。 以前保存的信息仍然有效。 向量改变位不影响向量寄存器的恢复，因此不会减少恢复时间。
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48.发明公开
公开(公告)号：EP0282213A2
公开(公告)日：1988-09-14
申请号：EP88301751.9
申请日：1988-03-01
申请人： AT&T Corp.
CPC分类号： G06F9/544 , G06F9/461 , G06F9/468 , G06F12/1036
摘要： There is disclosed a memory management arrangement which facilitates interprocess data transfers by eliminating the need to construct temporary mapping tables when performing the data transfer operation. The arrangement includes the use of multiple and concurrent mapping tables in conjunction with the transmission of mapping table identification bits with each data transfer operation.
摘要翻译： 公开了一种存储器管理装置，其通过在执行数据传送操作时消除构建临时映射表的需要来促进进程间数据传输。 该布置包括使用多个并发映射表与每个数据传送操作的映射表识别位的传输相结合。
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49.发明公开
公开(公告)号：EP0083002A2
公开(公告)日：1983-07-06
申请号：EP82111433.7
申请日：1982-12-09
IPC分类号： G06F3/04
CPC分类号： G06F9/461 , G06F13/385
摘要： An interrupt network whereby, upon completion of a data transfer cycle between a host computer and peripheral-controller or completion of a data transfer cycle between a peripheral terminal and peripheral-controller, the peripheral-controller is placed in an interrupt mode (background mode) and institutes an interrupt service routine. The normal mode data in the peripheral-controller is stored for re-use upon return to normal mode.
摘要翻译： 一种中断网络，在完成主计算机和外围控制器之间的数据传输周期或完成外围终端和外围控制器之间的数据传输周期之后，外围控制器被置于中断模式（背景模式） 并制定中断服务程序。 存储外围控制器中的正常模式数据，以便在返回正常模式时重新使用。
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50.发明授权
公开(公告)号：EP4288866B1
公开(公告)日：2024-10-09
申请号：EP22715296.4
申请日：2022-03-21
CPC分类号： G06F12/0269 , G06F9/4488 , G06F9/461
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