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公开(公告)号：EP0334443B1
公开(公告)日：1993-03-03
申请号：EP89200690.9
申请日：1989-03-20
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公开(公告)号：EP0336681A3
公开(公告)日：1992-08-26
申请号：EP89303273.0
申请日：1989-04-03
申请人： FUJITSU LIMITED
发明人： Abe, Masato , Asami, Fumitaka
CPC分类号： H03M5/18
摘要： A code converter includes:
extraction means (31) for extracting a reference level from a binary-coded input signal, which is offset at the predetermined voltage level and varies arbitrarily with the same polarity as the voltage level; twos-complement conversion means(32), connected to the extraction means (31),for converting the reference level into a twos-complement value; and creation means (33), connected to said extraction means (31) and twos-complement conversion means(32) for adding an output signal of the twos-complement conversion means (32) and the binary-coded input signal, thereby producing a bipolar binary-coded output signal to which a polarity bit is added.-
43.发明公开Binary-to-ternary converter for combining two binary signals 失效Binär-Ternär-Umsetzer zur Kombination von zweiBinär-Signalen。
公开(公告)号：EP0334443A1
公开(公告)日：1989-09-27
申请号：EP89200690.9
申请日：1989-03-20
摘要： For a binary-to-ternary converter fed from a standard TTL supply of 5 V ± 5%, a minimum 4.75 V supply voltage is available. According to the amplitude requirement of the CCITT Recommendation G703, the positive and negative output pulses should have an amplitude of 2.37 V± 10%.
A binary-to-ternary converter should be protected against high voltage-pulses from outside. This is achieved by serially connecting a protective resistance to the output. An unacceptable voltage loss will then develop through this arrangement.
The binary-to-ternary converter according to the invention satisfies the abovementioned requirements without utilizing a transformer, despite the fact that the overall voltage swing for the ternary output signal corresponds with a higher value than the worst-case 4.75 V supply voltage which is available.摘要翻译： 对于从5 V +/- 5％的标准TTL电源供电的二进制到三进制转换器，可提供最低4.75 V的电源电压。 根据CCITT建议书G703的幅度要求，正，负输出脉冲的幅度应为2.37V +/- 10％。 应保护二进制到三元转换器免受外部高电压脉冲的影响。 这是通过将保护电阻串联连接到输出来实现的。 然后通过这种布置发展不可接受的电压损失。 根据本发明的二进制到三元转换器满足上述要求而不使用变压器，尽管事实上三元输出信号的总体电压摆幅对应于比可用的最差情况4.75V电源电压更高的值 。
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44.发明公开Coding apparatus and magnetic recording system the same 失效Kodierungsgerätund diesesGerätverwendendes magnetisches Aufzeichnungssystem。
公开(公告)号：EP0319216A2
公开(公告)日：1989-06-07
申请号：EP88311224.5
申请日：1988-11-25
CPC分类号： H03M5/18 , H04L25/497
摘要： By transforming a duobinary signal, such cases are prohibited that a value of -1 is appeared again after a value of zero following -1 as shown in a string of -1 0 → -1 and a value of 1 is appeared again after a value of zero following 1 as shown in a string of 1 → 0 → 1. Narrow-band transmission is made possible by the fact that the direct current (DC) component of a duobinary signal can be eliminated without losing such natures thereof as to be ternary and reproducible original information by discriminating its even level as one (1) and its odd level as zero (0). Since the DC component can be eliminated, electromagnetic conversion systems are hardly subjected to distortion, leading to a reduction of probability of code errors.
摘要翻译： 通过转换双二进制信号，禁止在-1 -1之后的-1之后的零值后再次出现-1的值，并且在-1之后再次出现值1 值为0，如1 - > 0 - > 1的串所示。通过以下事实可以实现窄带传输：双二进制信号的直流（DC）分量可以消除，而不会失去其性质 通过将其平均电平区分为一（1）和其奇数电平为零（0）来进行三元和可再现的原始信息。 由于可以消除DC分量，因此电磁转换系统几乎不会发生变形，导致代码错误的概率降低。
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公开(公告)号：EP0226351A2
公开(公告)日：1987-06-24
申请号：EP86309146.8
申请日：1986-11-24
发明人： Kong, Samuel
IPC分类号： H03M5/18
CPC分类号： G01R19/16557
摘要： A three-voltage level detector include an input node for receiving an input logic signal having either a high level, mid-level or low level voltage. A first level sensing buffer is responsive to the input logic signal for generating a first output sense voltage indicative of whether the input logic signal is either at the (a) high level voltage or (b) mid-level or low level voltage. A second level sensing buffer is responsive to the input logic signal for generating a second output sense voltage indicative of whether the input logic signal is either at the (a) high level or mid-level voltage or (b) low level voltage. Logic gate circuits are responsive to the first and second output sense voltages for generating a first output signal being in a high level only when the input logic signal is at the high level voltage, a second output signal being in a high level only when the input logic signal is at the low level voltage, a third output signal being in a high level only the input logic signal is at the mid-level voltage.
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46.发明公开Frequency-independent, self-clocking encoding technique and apparatus for digital communications 失效常见问题解答，selbsttaktierende Kodierungstechnik und Einrichtungfürdigitale Kommunikation。
公开(公告)号：EP0074587A2
公开(公告)日：1983-03-23
申请号：EP82108162.7
申请日：1982-09-03
CPC分类号： H04L25/4904 , H03M5/18 , H04L25/4925
摘要： A self-clocking encoding technique for synchronous transmission of digital signals, and apparatus therefor. In an exemplary embodiment, the encoding technique utilizes relatively positive and relatively negative pulses of fixed, predetermined duration. For electrical pulses, the point of reference is preferably a zero baseline. At the leading edge LE, of the i th bit cell, the value of the i th bit is encoded as a positive pulse in the case of a logical "1" (e.g., 82A) or a negative pulse (e.g., 82B) in the case of a logical "0" (Step 41, 42A, 428). Further, if the next subsequent (i.e., (i + 1) th bit has the same value, a pulse of the opposite polarity is injected into the i th bit cell after the leading edge pulse (e.g., 82D). Thus, positive and negative pulses alternate and the information content of the encoded signal has no d.c. component; this facilitates a.c. coupling. Further, the encoding technique is bit-rate (i.e., frequency-) independent and usable over a wide range of bit transfer rates. The receiver can synchronously decode the signal if it knows the pulse width; it need not know the sender's transmission rate and indeed, bit transmission rate may even change from one bit cell to the next.
For a fiber optic implementation, a non-zero baseline is used. The optical zero output level replaces the electrical negative pulse level, the half-maximum optical output level replaces the electrical zero level and the maximum optical output level replaces the electrically positive pulse.摘要翻译： 一种用于数字信号的同步传输的自定时编码技术及其装置。 在示例性实施例中，编码技术利用固定的预定持续时间的相对正和负脉冲。 对于电脉冲，参考点优选为零基线。 在第i个位单元的前沿LEi，在逻辑“0”的情况下，第i位的值被编码为正脉冲，在逻辑“0”的情况下，被编码为正脉冲。 此外，下一个后续（即，第（i + 1）位具有相同的值，相反极性的脉冲（例如，82D）在前沿脉冲之后被注入到第i个位单元中，因此，正和负脉冲 编码信号的信息内容没有直流分量，这有助于交流耦合，而且编码技术是比特率（即频率）独立的，可以在宽范围的比特传输速率下使用，接收机可以同步 如果它知道脉冲宽度，则对信号进行解码;它不需要知道发送器的传输速率，实际上，比特传输速率甚至可能从一个比特单元变为下一个。对于光纤实现，使用非零基线。 光学零输出电平取代电负脉冲电平，半最大光输出电平取代电零电平，最大光输出电平取代电正脉冲。
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公开(公告)号：EP3780526A1
公开(公告)日：2021-02-17
申请号：EP19306015.9
申请日：2019-08-14
申请人： NXP USA, Inc.
摘要： A battery management system comprises a first battery cell controller; a second
battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller. At least one of the first battery cell controller or the second battery cell controller includes at least one encoding/ decoding circuit for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique, including modulating the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency, encoding a plurality of data nibbles of the serial data stream into a data packet, the data packet including a plurality of symbols constructed and arranged with at least four consecutive chips per symbol, wherein the at least four consecutive chips per symbol of the data packet includes a DC balanced line code in each of the symbols.-
公开(公告)号：EP2621099B1
公开(公告)日：2016-04-20
申请号：EP12195027.3
申请日：2012-11-30
申请人： FUJITSU LIMITED
发明人： Nakasha, Yasuhiro , Hayashi, Hiroki , Itoh, Takumi
CPC分类号： H04L25/03 , H03K5/12 , H03M5/16 , H04B1/71635 , H04B1/7172 , H04B1/7174
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公开(公告)号：EP2621099A1
公开(公告)日：2013-07-31
申请号：EP12195027.3
申请日：2012-11-30
申请人： FUJITSU LIMITED
发明人： Nakasha, Yasuhiro , Hayashi, Hiroki , Itoh, Takumi
IPC分类号： H04B1/7163 , H04B1/717 , H04L25/49 , H04L27/04 , H03M5/18
CPC分类号： H04L25/03 , H03K5/12 , H03M5/16 , H04B1/71635 , H04B1/7172 , H04B1/7174
摘要： A communication device includes: a converting part converting a data signal from a non-return-to-zero signal to a return-to-zero signal; a trigger flip-flop inverting an output signal every time the return-to-zero signal changes in one cycle; a first filter outputting a positive pulse and a negative pulse alternately, which indicate existence and absence of the pulse corresponding to a value of the data signal, by removing a low frequency component of an output signal of the trigger flip-flop.
摘要翻译： 通信装置包括：转换部分，将数据信号从非归零信号转换为归零信号; 每次在一个周期内返回零信号变化时，触发触发器反相输出信号; 通过去除触发器触发器的输出信号的低频分量，交替地输出正脉冲和负脉冲的第一滤波器，其指示与数据信号的值相对应的脉冲的存在和不存在。
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