公开(公告)号：EP0318814A2

公开(公告)日：1989-06-07

申请号：EP88119504.4

申请日：1988-11-23

申请人： ADVANTEST CORPORATION

发明人： Sato, Kazuhiko ,  Nishiura, Junji ,  Takahashi, Keiichi

IPC分类号： G01R31/28 ,  G06F11/26

CPC分类号： G01R19/16557 ,  G01R31/31935 ,  G01R31/31937

摘要： Supplied with an output response signal from a circuit un­der test in each test channel, a level comparator (300) compares the signal with a reference level which defines a normal logical level, and the compared output is applied to two independent signal detectors (402, 403), wherein it is detected and held at the timing of two strobe pulses (STRB1, STRB2) which are provided thereto via two different signal lines (415, 416) at a desired time interval. These detected signals are applied to two logical comparators (401A, 401B), wherein they are compared with expected value signals, respectively. An expected value signal switching circuit may be provided by which the expected value signal in this test channel and the expected value signal in an­other test channel are selectively provided to one of the logical comparators. It is also possible to adopt an arran­gement in which test results read out of a plurality of storage areas of a failure analysis memory are provided as mask data to a desired one of the logical comparators to thereby mask its logical comparison.

摘要翻译： 在每个测试通道中提供来自被测电路的输出响应信号，电平比较器（300）将该信号与定义正常逻辑电平的参考电平进行比较，并将比较的输出施加到两个独立的信号检测器（402， 403），其中在期望的时间间隔经由两条不同信号线（415,416）向其提供的两个选通脉冲（STRB1，STRB2）的定时处检测并保持它。 这些检测到的信号被施加到两个逻辑比较器（401A，401B），其中它们分别与期望值信号进行比较。 可以提供期望值信号切换电路，通过该期望值信号切换电路，将该测试信道中的期望值信号和另一测试信道中的期望值信号选择性地提供给逻辑比较器中的一个。 也可以采用从故障分析存储器的多个存储区读出的测试结果作为掩码数据提供给所需的一个逻辑比较器，从而掩盖其逻辑比较。

公开(公告)号：EP0169754A1

公开(公告)日：1986-01-29

申请号：EP85401210.1

申请日：1985-06-18

申请人： THOMSON-CSF

发明人： Berger, Jean-Luc

IPC分类号： G01R19/165 ,  G11C19/28 ,  H01L29/78 ,  H03F3/70 ,  H03K3/353 ,  G01R29/24

CPC分类号： G01R19/16557 ,  G11C19/285 ,  H01L29/768 ,  H03F3/70 ,  H03K3/353

摘要： La présente invention concerne un comparateur analogique à transfert de charge comportant deux capacités MIS (1, 2) adjacentes, couplées entre elles par une grille de passage (Gp) et reliées respectivement à l'entrée et à la sortie d'un amplificateur (A) ainsi qu'un moyen (T o ) d'initialisation de la comparaison relié à l'entrée de l'amplificateur et des moyens pour introduire sous chaque capacité respectivement la charge-signal et la charge de référence.
Application dans les convertisseurs analogiques- numériques ou dans les calibrateurs analogiques.

公开(公告)号：EP0067510A3

公开(公告)日：1984-08-22

申请号：EP82302172

申请日：1982-04-28

申请人： JOHN FLUKE MFG. CO., INC.

发明人： Bhaskar, Kasi Seshadri ,  Carlson, Alden J. ,  Couper, Alastair Norman ,  Lambert, Dennis L. ,  Scott, Marshall H.

IPC分类号： G06F11/26 ,  G01R31/28

CPC分类号： G06F11/261 ,  G01R19/16557 ,  G01R31/31912 ,  G06F11/2221 ,  G06F11/2257 ,  G06F11/2273 ,  G06F11/2736 ,  G06F11/32 ,  G06F11/325

摘要： AA microprocessor-based test system for functionally testing and troubleshooting microprocessor-based systems is connected in place of the microprocessor circuit of the unit 18 being tested (UUT). The test system includes a microprocessor circuit 42 which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT 18. The test system periodically switches this microprocessor 42 into signal communication with the UUT 18 for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit 42 is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/0 registers 26, 28 and 30.

公开(公告)号：EP2530476A3

公开(公告)日：2014-10-15

申请号：EP11190306.8

申请日：2011-11-23

申请人： Actron Technology Corporation

发明人： Liu, Tung-Jung

IPC分类号： G01R19/165

CPC分类号： G01R19/1658 ,  G01R19/16538 ,  G01R19/16557

摘要： A phase detection apparatus (2) for an alternator is disclosed according to an embodiment of the present invention. The phase detection apparatus (2) comprises a waveform detector (21), a threshold voltage generator (22), and a comparator (23). The waveform detector (21) is used for detecting a wave peak of a phase signal, and generating a waveform detection signal accordingly. The threshold voltage generator (22) is used for generating a reference signal according to the waveform detection signal. The comparator (23) is used for comparing the phase signal with the reference signal, and generating a comparison signal accordingly. Therefore, the phase detection apparatus (2) for the alternator may reduce the leakage current of a battery in a vehicle.

公开(公告)号：EP2530476A2

公开(公告)日：2012-12-05

申请号：EP11190306.8

申请日：2011-11-23

申请人： Actron Technology Corporation

发明人： Liu, Tung-Jung

IPC分类号： G01R19/165

CPC分类号： G01R19/1658 ,  G01R19/16538 ,  G01R19/16557

摘要： A phase detection apparatus (2) for an alternator is disclosed according to an embodiment of the present invention. The phase detection apparatus (2) comprises a waveform detector (21), a threshold voltage generator (22), and a comparator (23). The waveform detector (21) is used for detecting a wave peak of a phase signal, and generating a waveform detection signal accordingly. The threshold voltage generator (22) is used for generating a reference signal according to the waveform detection signal. The comparator (23) is used for comparing the phase signal with the reference signal, and generating a comparison signal accordingly. Therefore, the phase detection apparatus (2) for the alternator may reduce the leakage current of a battery in a vehicle.

摘要翻译： 根据本发明的实施例公开了一种用于交流发电机的相位检测装置（2）。 相位检测装置（2）包括波形检测器（21），阈值电压发生器（22）和比较器（23）。 波形检测器（21）用于检测相位信号的波峰，并相应地产生波形检测信号。 阈值电压发生器（22）用于根据波形检测信号产生参考信号。 比较器（23）用于将相位信号与参考信号进行比较，并相应地产生比较信号。 因此，用于交流发电机的相位检测装置（2）可以减少车辆中的电池的泄漏电流。

公开(公告)号：EP0318814B1

公开(公告)日：1994-03-09

申请号：EP88119504.4

申请日：1988-11-23

申请人： ADVANTEST CORPORATION

发明人： Sato, Kazuhiko ,  Nishiura, Junji ,  Takahashi, Keiichi

IPC分类号： G01R31/28 ,  G06F11/26

CPC分类号： G01R19/16557 ,  G01R31/31935 ,  G01R31/31937

摘要： Supplied with an output response signal from a circuit under test in each test channel, a level comparator (300) compares the signal with a reference level which defines a normal logical level, and the compared output is applied to two independent signal detectors (402, 403), wherein it is detected and held at the timing of two strobe pulses (STRB1, STRB2) which are provided thereto via two different signal lines (415, 416) at a desired time interval. These detected signals are applied to two logical comparators (401A, 401B), wherein they are compared with expected value signals, respectively. An expected value signal switching circuit may be provided by which the expected value signal in this test channel and the expected value signal in another test channel are selectively provided to one of the logical comparators. It is also possible to adopt an arrangement in which test results read out of a plurality of storage areas of a failure analysis memory are provided as mask data to a desired one of the logical comparators to thereby mask its logical comparison.

摘要翻译： 在每个测试通道中提供来自被测电路的输出响应信号，电平比较器（300）将该信号与定义正常逻辑电平的参考电平进行比较，并将比较的输出施加到两个独立的信号检测器（402， 403），其中在期望的时间间隔经由两条不同信号线（415,416）向其提供的两个选通脉冲（STRB1，STRB2）的定时处检测并保持它。 这些检测到的信号被施加到两个逻辑比较器（401A，401B），其中它们分别与期望值信号进行比较。 可以提供期望值信号切换电路，通过该期望值信号切换电路，将该测试信道中的期望值信号和另一测试信道中的期望值信号选择性地提供给逻辑比较器中的一个。 也可以采用从故障分析存储器的多个存储区读出的测试结果作为掩码数据提供给所需的一个逻辑比较器，从而掩盖其逻辑比较。

公开(公告)号：EP0289370B1

公开(公告)日：1992-07-29

申请号：EP88400663.6

申请日：1988-03-18

申请人： SGS-THOMSON MICROELECTRONICS S.A.

发明人： Kowalski, Jacek ,  Chevallier, Christophe Jean François

IPC分类号： G01R19/165

CPC分类号： G01R19/16557 ,  G01R19/16519

公开(公告)号：EP0182388B1

公开(公告)日：1989-08-16

申请号：EP85114975.7

申请日：1982-04-28

申请人： JOHN FLUKE MFG. CO., INC.

发明人： Bhaskar, Kasi Seshadri c/o John Fluke Mfg Co. Ltd. ,  Carlson, Alden J. ,  Couper, Alastair Norman ,  Lambert, Dennis L. ,  Scott, Marshall H.

IPC分类号： G01R31/28

CPC分类号： G06F11/261 ,  G01R19/16557 ,  G01R31/31912 ,  G06F11/2221 ,  G06F11/2257 ,  G06F11/2273 ,  G06F11/2736 ,  G06F11/32 ,  G06F11/325

公开(公告)号：EP0254012A3

公开(公告)日：1989-07-12

申请号：EP87108417.4

申请日：1987-06-11

申请人： TEKTRONIX, INC.

发明人： Branson, Christopher Warren ,  Sullivan, Steven Kent

IPC分类号： G01R31/28 ,  G01R31/318

CPC分类号： G01R31/31924 ,  G01R19/16557

摘要： An active load network for a device under test includes a logic circuit for anticipating the out­put state of the device under test and for turning on either a current source of a current sink to properly load its output. The current sink and current source each comprise a pair of CMOS transistors connected in series. One of each transistor pair turns on to either source or sink current and the other provides a variable impedance controlled by the voltage at its gate to regulate the amount of current. A pull-to-­center transmission gate is also provided which pulls the output of the device under test to a level between a logic high and logic low when it is turned off.

公开(公告)号：EP0102618A3

公开(公告)日：1987-07-29

申请号：EP83108582

申请日：1983-08-31

申请人： NEC CORPORATION

发明人： Watanabe, Takayuki

IPC分类号： G11C05/00 ,  G11C08/00 ,  G01R19/165 ,  G05F01/571 ,  G06F01/00 ,  H03K17/22

CPC分类号： H03K17/223 ,  G01R19/16557 ,  G05F1/571 ,  G06F1/28 ,  G11C5/143 ,  G11C8/18

摘要： @ A memory circuit provided with a control circuit which controls operations of the memory circuit in such a manner that the memory circuit is automatically set in a stand-by state when a value of a power voltage is reduced in absolute value irrespectively of a control signal from the outside and which consumes no DC current is disclosed. The control circuit comprises a load element coupled between first and second terminals, a series circuit of first and second field effect transistors coupled between the second terminal and a third terminal, the first transistor being controlled by the control signal, the second transistor being adapted to be conducting when a value of the power voltage is sufficient for allowing a normal access operation, a means for connecting the first terminal to one of the power voltage and a reference voltage, and a means for connecting the third terminal to the other of the power voltage and the reference voltage.