NETWORK ON A CHIP SOCKET PROTOCOL
    56.
    发明公开

    公开(公告)号:EP4123468A1

    公开(公告)日:2023-01-25

    申请号:EP22196229.3

    申请日:2013-09-24

    摘要: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

    MEMS PROCESS POWER
    57.
    发明公开
    MEMS PROCESS POWER 审中-公开

    公开(公告)号:EP4106189A1

    公开(公告)日:2022-12-21

    申请号:EP22163261.5

    申请日:2016-04-22

    IPC分类号: H03H9/17 G11B9/00 H01L41/08

    摘要: A transducer includes a first piezoelectric layer; and a second piezoelectric layer that is above the first piezoelectric layer; wherein the second piezoelectric layer is a more compressive layer with an average stress that is less than or more compressive than an average stress of the first piezoelectric layer.

    MOS TRANSISTOR OFFSET-CANCELLING DIFFERENTIAL CURRENT-LATCHED SENSE AMPLIFIER

    公开(公告)号:EP3516654A1

    公开(公告)日:2019-07-31

    申请号:EP17772855.7

    申请日:2017-09-18

    IPC分类号: G11C7/06 G11C11/16 G11C7/08

    摘要: Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify received differential data and reference input voltages with a smaller sense amplifier offset voltage to provide larger sense margin between different storage states of memory bitcell(s). The OCZS-SA is configured to cancel out offset voltages of input and complement input transistors, and keep the input and complement input transistors in their activated state during sensing phases so that sensing is not performed in their “dead zones” when their gate-to-source voltage (Vgs) is below their respective threshold voltages. In other aspects, sense amplifier capacitors are configured to directly store the data and reference input voltages at gates of the input and complement input transistors during voltage capture phases to avoid additional layout area that would otherwise be consumed with additional sensing capacitor circuits.