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公开(公告)号：EP3516654B1
公开(公告)日：2020-10-21
申请号：EP17772855.7
申请日：2017-09-18
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公开(公告)号：EP3516654A1
公开(公告)日：2019-07-31
申请号：EP17772855.7
申请日：2017-09-18
摘要： Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify received differential data and reference input voltages with a smaller sense amplifier offset voltage to provide larger sense margin between different storage states of memory bitcell(s). The OCZS-SA is configured to cancel out offset voltages of input and complement input transistors, and keep the input and complement input transistors in their activated state during sensing phases so that sensing is not performed in their “dead zones” when their gate-to-source voltage (Vgs) is below their respective threshold voltages. In other aspects, sense amplifier capacitors are configured to directly store the data and reference input voltages at gates of the input and complement input transistors during voltage capture phases to avoid additional layout area that would otherwise be consumed with additional sensing capacitor circuits.
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公开(公告)号：EP3143622B1
公开(公告)日：2018-10-03
申请号：EP15730011.2
申请日：2015-06-04
IPC分类号： G11C8/14 , G11C11/412 , G11C11/419 , G11C7/20
CPC分类号： G11C11/419 , G11C5/02 , G11C7/00 , G11C7/20 , G11C8/14 , G11C8/16 , G11C11/412 , G11C11/417
摘要： A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.
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4.发明公开SYSTEM AND METHOD OF SENSING A MEMORY CELL 审中-公开LESEN EINER SPEICHERZELLE MIT REFERENZSPEICHERZELLE UND GEMEINSAMEN ABTAST-PFAD
公开(公告)号：EP2973575A2
公开(公告)日：2016-01-20
申请号：EP14714539.5
申请日：2014-03-12
发明人： JUNG, Seong-Ook , NA, Taehui , KIM, Jisu , KANG, Seung H. , KIM, Jung Pill
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1693 , G11C13/004 , G11C27/024 , G11C2013/0054 , G11C2013/0057 , G11C2207/002
摘要： A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.
摘要翻译： 一种方法包括感测数据单元的状态以产生数据电压。 数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。 该方法还包括感测参考单元的状态以产生参考电压。 通过公共感测路径来检测数据单元的状态和参考单元的状态。 该方法还包括基于数据电压和参考电压来确定数据单元的逻辑值。
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公开(公告)号：EP2973575B1
公开(公告)日：2018-10-24
申请号：EP14714539.5
申请日：2014-03-12
发明人： JUNG, Seong-Ook , NA, Taehui , KIM, Jisu , KANG, Seung H. , KIM, Jung Pill
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1693 , G11C13/004 , G11C27/024 , G11C2013/0054 , G11C2013/0057 , G11C2207/002
摘要： A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.
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公开(公告)号：EP3350930A1
公开(公告)日：2018-07-25
申请号：EP16763625.7
申请日：2016-08-25
发明人： JUNG, Seong-Ook , CHOI, Sara , SONG, Byung Kyu , NA, Taehui , KIM, Jisu , KIM, Jung Pill , KIM, Sungryul , KIM, Taehyun , KANG, Seung Hyuk
CPC分类号： H03M13/616 , G06F11/10 , G06F11/1012 , H03M13/152 , H03M13/1575 , H03M13/617 , H03M13/6502
摘要： Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.
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7.发明授权SRAM READ BUFFER WITH REDUCED SENSING DELAY AND IMPROVED SENSING MARGIN 有权SRAM读缓冲器具有降低的感测延迟和改进的感测裕量
公开(公告)号：EP3028281B1
公开(公告)日：2017-12-20
申请号：EP14748067.7
申请日：2014-07-21
IPC分类号： G11C11/412
CPC分类号： G11C11/419 , G06F17/5072 , G11C8/16 , G11C11/412
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公开(公告)号：EP3039684A1
公开(公告)日：2016-07-06
申请号：EP14750037.5
申请日：2014-07-09
发明人： JUNG, Seong-Ook , NA, Taehui , KIM, Jisu , KIM, Jung Pill , KANG, Seung Hyuk
CPC分类号： G11C11/1673 , G11C7/06 , G11C7/065 , G11C11/1693 , G11C13/004 , G11C2013/0054 , G11C2013/0057
摘要： An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.
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9.发明公开SRAM READ BUFFER WITH REDUCED SENSING DELAY AND IMPROVED SENSING MARGIN 有权SRAM-LESEPUFFER MIT REDUZIERTERMESSVERZÖGERUNGUNDERHÖHTERMESSMARGE
公开(公告)号：EP3028281A1
公开(公告)日：2016-06-08
申请号：EP14748067.7
申请日：2014-07-21
IPC分类号： G11C11/412
CPC分类号： G11C11/419 , G06F17/5072 , G11C8/16 , G11C11/412
摘要： A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.
摘要翻译： 一种器件包括静态随机存取存储器（SRAM）单元和耦合到SRAM单元的输出的读缓冲器。 读缓冲器包括一个反相器和一个开关。 反相器的输入响应于SRAM单元的输出。 开关的控制端子响应于逆变器的输出。
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公开(公告)号：EP2727111B1
公开(公告)日：2018-05-09
申请号：EP12736005.5
申请日：2012-07-01
发明人： JUNG, Seong-Ook , KIM, Jisu , RYU, Kyungho , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C16/26 , G11C7/06 , G11C7/12 , G11C11/16 , G11C11/4091
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C16/26
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.
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