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51.发明公开ASSOCIATIVE MEMORY, ITS RETRIEVAL METHOD, ROUTER, AND NETWORK SYSTEM 审中-公开INHALTSADRESSIERBARER SPEICHER，WIEDERAUFFFINDUNGSVERFAHREN，ROUTER UND NETZWERKSYSTEM
公开(公告)号：EP1300854A1
公开(公告)日：2003-04-09
申请号：EP01936815.8
申请日：2001-05-30
发明人： OGURA, Naoyuki
摘要： When one or more storage data are coincident with single search data (12), an associative memory (1) carries out logical sum for all of storage data with a valid state for storage data as true. The result of logical sum is used as matched data logical-OR information. In a primary searching operation, the associative memory (1) is supplied with the search data (12) to provide the matched data logical-OR information on matched data logical-OR lines. Then, the associative memory (1) carries out a secondary searching operation supplied as search data with the matched data logical-OR information obtained by all of storage data coincident upon the primary searching operation. Only a match line (5) coincident with the matched data logical-OR information is selected as the secondary search result. The associative memory is used in a network router to calculate an optimum memory address signal (403) by encoding the selected match line (5). In response to the memory address signal (403), a memory data signal (405) enabling shortest network connection is produced as a transfer network address (413). The transfer network address (413) is combined with a data area (412) and a destination network address (411) contained in input transfer data (408) to produce output transfer data (409).
摘要翻译： 当一个或多个存储数据与单个搜索数据（12）一致时，关联存储器（1）对于存储数据的有效状态的所有存储数据执行逻辑和，为真。 逻辑和的结果用作匹配数据逻辑或信息。 在主要搜索操作中，向联想存储器（1）提供搜索数据（12）以在匹配的数据逻辑或线上提供匹配的数据逻辑或信息。 然后，关联存储器（1）执行辅助搜索操作，作为搜索数据提供具有与主搜索操作一致的所有存储数据获得的匹配数据逻辑或信息。 仅选择与匹配数据逻辑或信息一致的匹配线（5）作为辅助搜索结果。 在网络路由器中使用关联存储器来通过对所选匹配线（5）进行编码来计算最佳存储器地址信号（403）。 响应于存储器地址信号（403），产生实现最短网络连接的存储器数据信号（405）作为传送网络地址（413）。 传输网络地址（413）与包含在输入传送数据（408）中的数据区（412）和目的地网络地址（411）组合以产生输出传输数据（409）。
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公开(公告)号：EP1296334A2
公开(公告)日：2003-03-26
申请号：EP02250682.8
申请日：2002-01-31
申请人： FUJITSU LIMITED
摘要： This associative memory circuit comprises a plurality of logic circuits connected to a common match line (12). Each of the logic circuits (Q1-Q4) compares a content stored in each of a plurality of memory cells (10 1 , 10 2 , ...) with externally supplied search data so as to output a comparison result thereof to the match line (12). The associative memory circuit also comprises a reference-potential producing circuit (22) provided correspondingly for the match line (12) so as to produce a reference potential used in relation with the match line (12), and a differential amplifier circuit (20) performing a differential amplification to a potential of the match line (12) and the reference potential so as to judge whether or not the content matches the search data.
摘要翻译： 该关联存储器电路包括连接到公共匹配线（12）的多个逻辑电路。 每个逻辑电路（Q1-Q4）将存储在多个存储单元（101,102，...）中的每一个的内容与外部提供的搜索数据进行比较，以便将其比较结果输出到匹配线（12 ）。 关联存储器电路还包括相应于匹配线（12）设置的参考电位产生电路（22），以产生与匹配线（12）相关的参考电位，以及差分放大电路（20） 对所述匹配线（12）的电位和所述参考电位进行差分放大，以便判断所述内容是否匹配所述搜索数据。
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53.发明公开Associative memory with AND gate match signal combining circuitry 有权Inhaltsadressierbarer Speicher mit And Gatter Ubereinstimmungssignalkombinationsschaltung
公开(公告)号：EP1271548A1
公开(公告)日：2003-01-02
申请号：EP01305439.0
申请日：2001-06-22
发明人： Barnes, William
摘要： An associative memory comprises an array of memory cells arranged in rows and columns, each row comprising a plurality of segments each of which comprises a set of said memory cells, wherein each memory cell has compare circuitry for comparing input data with data stored therein and for generating a cell match signal when said input data matches said stored data and match signal combining circuitry for receiving a match signal from a preceding cell in the set and operable to generate a logical value dependent on the match signal of the current cell and the match signal of the preceding cell whereby each segment generates a resultant segment logical value, the memory further comprising combinatorial logic circuitry associated with each row for combining said resultant segment logical values to generate a final output match signal for that row.
摘要翻译： 相关存储器包括以行和列排列的存储器单元的阵列，每行包括多个段，每个段包括一组所述存储单元，其中每个存储单元具有用于将输入数据与存储在其中的数据进行比较的比较电路， 当所述输入数据与所述存储的数据匹配并且匹配信号组合电路用于从所述组中的先前小区接收匹配信号并且可操作以产生取决于当前小区的匹配信号和匹配信号的逻辑值时，产生小区匹配信号 其中每个段产生合成段逻辑值，所述存储器还包括与每行相关联的组合逻辑电路，用于组合所述合成段逻辑值以产生该行的最终输出匹配信号。
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公开(公告)号：EP1227497A1
公开(公告)日：2002-07-31
申请号：EP02000985.8
申请日：2002-01-16
摘要： This invention provides an associative memory composed of plural chips or a single chip which is preferably used in the fields of bandwidth compression for video images in mobile communication terminals and artificial intelligence systems. The associative memory is a small-area associative memory formed using CMOS technology with a fast parallel minimum-distance-search capability. The transistor number of the provided search circuit is only linear proportional to the number of rows of the associative memory. Therefore, the increase in the number of required circuits is small even if the unit number of the input data or the unit number of the reference data is large. With the associative memory, it is possible to realize the functions of video signal compression and object recognition necessary for artificial intelligence systems, data bank systems and mobile network terminals with a single chip or plural chips.
摘要翻译： 本发明提供一种由移动通信终端和人造智能系统中的视频图像的带宽压缩领域中优选使用的多个芯片或单个芯片组成的关联存储器。 关联存储器是使用具有快速并行最小距离搜索能力的CMOS技术形成的小面积关联存储器。 所提供的搜索电路的晶体管数量仅与关联存储器的行数成线性比例。 因此，即使输入数据的单位数或参考数据的单位数量大，所需电路数量的增加也很小。 利用关联存储器，可以实现具有单个芯片或多个芯片的人造智能系统，数据库系统和移动网络终端所必需的视频信号压缩和对象识别的功能。
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55.发明公开A content addressable memory (CAM) for data lookups in a data processing system 有权内容寻址存储器（CAM），用于数据处理系统中的数据查询
公开(公告)号：EP1191540A2
公开(公告)日：2002-03-27
申请号：EP01120228.0
申请日：2001-08-23
发明人： Helwig, Klaus
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： The invention regards a content addressable memory, which, for example, may be implemented in a data processing system or a data processor and comprises at least a first single bit storage (101; 301), a word line (WL), at least one bit write line (BLWT, BLWC) and a hit/miss line (H/M), and at least a first single bit compare circuit (201; 320), said first single bit storage comprises at least a first output (A; A0) and said first single bit compare circuit comprises at least a first compare bit input (BLCT; CB 0) and two field effect transistors (113, 114; 312, 313).
Particularly, in order to reduce the power consumption, said first output (A; A0) of said single bit storage (101; 301) is applied to the gate of only one, a first field effect transistor (114; 312) of said two field effect transistors (113, 114; 312, 313). For an additional reduction of the power consumption two single bit storages (101, 301) are connected to a shared compare circuit (319). In case of a mismatch, only one out of four compare nodes (C0, C1, C2, C3) of the shared compare circuit is switched high, i.e. changes its potential.摘要翻译： 本发明涉及一种内容可寻址存储器，其例如可以在数据处理系统或数据处理器中实现，并且至少包括第一单个位存储器（101; 301），字线（WL），至少一个 所述第一单比特存储器包括至少一个第一输出端（A; A0），所述第一单比特存储器单元包括至少一个第一输出端（A0，A0，A0，A0，A0） ）并且所述第一单比特比较电路至少包括第一比较比特输入（BLCT; CB 0）和两个场效应晶体管（113,114; 312,313）。 特别地，为了降低功耗，所述单个位存储器（101; 301）的所述第一输出（A; A0）被施加到所述两个单元的所述两个第一场效应晶体管（114; 312） 场效应晶体管（113,114; 312,313）。 为了额外减少功耗，两个单位存储器（101,301）连接到共享比较电路（319）。 在不匹配的情况下，共享比较电路的四个比较节点（C0，C1，C2，C3）中只有一个切换为高电平，即改变其电位。
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公开(公告)号：EP1155415A1
公开(公告)日：2001-11-21
申请号：EP99934849.3
申请日：1999-07-15
IPC分类号： G11C15/04
CPC分类号： G06F17/30982 , G11C15/04
摘要： A content addressable memory comprises a CAM control logic unit (11) and a plurality of cells (10) connected in a chain. Each cell comprises a memory block (12) coupled to a common address bus (ADD), a comparator (14) coupled to a common data bus (DATA) and to the data interface of the memory block (12), switching means (15) coupling the data interface of the memory block with the data bus, and a logic block (13) including a Match flip-flop (16). The memory is operable in two phases, a Search phase and an Access phase. In the Search phase, a sequence of words on the common data bus (DATA) is serially matched with the contents of a sequence of addresses in the memory blocks (12) of the cells (10). In the Access phase, the cells matched in the Search phase are made serially available for access via the common address and data buses (ADD and DATA).
摘要翻译： 内容可寻址存储器包括CAM控制逻辑单元（11）和以链条连接的多个单元（10）。 每个单元包括耦合到公共地址总线（ADD）的存储器块（12），耦合到公共数据总线（DATA）和存储器块（12）的数据接口的比较器（14），开关装置 ）将存储器块的数据接口与数据总线耦合，以及包括匹配触发器（16）的逻辑块（13）。 内存可以分两个阶段进行操作，即搜索阶段和访问阶段。 在搜索阶段，公共数据总线（DATA）上的字序列与单元（10）的存储块（12）中的地址序列的内容串行匹配。 在访问阶段，在搜索阶段匹配的单元通过公共地址和数据总线（ADD和DATA）可串行访问。
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57.发明公开Three port content addressable memory device and methods for implementing the same 审中-公开Dreitorige inhaltsadressierbare Speicheranordnung und Methoden ihrer Implementierung
公开(公告)号：EP1083572A1
公开(公告)日：2001-03-14
申请号：EP00307752.6
申请日：2000-09-08
CPC分类号： G11C29/816 , G11C8/16 , G11C15/00 , G11C15/04 , G11C29/14 , G11C2029/2602
摘要： A three-port content addressable memory (CAM) device and method thereof are provided. The three-port CAM device includes a CAM, a search control block, and a maintenance control block. The CAM is configured to store data. The search control block is arranged to receive search data and search control signals via a first port for searching the search data in the CAM. The search control block is further configured to perform search operations by accessing the CAM. The search operations are performed within search cycles with each search operation being performed over multiple clock cycles. In this configuration, more than one search operations are capable of being performed simultaneously over one or more clock cycles. Search results of the search operations are output via a second port. The maintenance control block is configured to perform read/write operations by reading or writing specified data in the CAM via a third port.
摘要翻译： 提供了一种三端口内容可寻址存储器（CAM）装置及其方法。 三端口CAM设备包括CAM，搜索控制块和维护控制块。 CAM配置为存储数据。 搜索控制块被布置成经由用于搜索CAM中的搜索数据的第一端口接收搜索数据和搜索控制信号。 搜索控制块还被配置为通过访问CAM执行搜索操作。 在搜索周期内执行搜索操作，每个搜索操作在多个时钟周期内执行。 在该配置中，可以在一个或多个时钟周期上同时执行多于一个的搜索操作。 通过第二个端口输出搜索操作的搜索结果。 维护控制块被配置为通过经由第三端口读取或写入CAM中的指定数据来执行读/写操作。
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公开(公告)号：EP1054407A1
公开(公告)日：2000-11-22
申请号：EP00110217.7
申请日：2000-05-17
CPC分类号： G11C15/04
摘要： A CAM memory is supplied targeted at storing data words whose bits can take on an indifferent logical value besides two complementary logical values. it includes a matrix (MA) of memory cells in which a pair of cells is assigned to each bit that can take on a ternary configuration, circuits (CT1 ... CT3, WR, SR; CT11 ... SR1, CT21 ... SR2) for memory (MA) matrix access control give access for performing comparisons during operation in the CAM mode or for writing/reading data by means of direct RAM mode addressing.
摘要翻译： 提供CAM存储器，其目的在于存储除了两个互补逻辑值之外，其位可以处于无关的逻辑值的数据字。 它包括一个存储单元的矩阵（MA），其中一对单元被分配给可以承载三进制配置的每个位，电路（CT1 ... CT3，WR，SR; CT11 ... SR1，CT21 .. 用于存储器（MA）矩阵访问控制的SR2用于在CAM模式下操作期间执行比较或通过直接RAM模式寻址来写入/读取数据的访问。
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公开(公告)号：EP1029277A1
公开(公告)日：2000-08-23
申请号：EP98958578.1
申请日：1998-11-13
CPC分类号： G06F17/30982 , G11C15/00 , G11C15/04 , Y10S707/99931 , Y10S707/99933
摘要： A content addressable memory ('CAM') engine (100) or controller interfaces between a host signal processor (e.g., a microprocessor) and a plurality of known, commercially-available random access memory ('RAM') devices. The CAM engine (100) configures the RAM as content addressable memory, thereby causing the normally location-addressd RAM to function as CAM. The CAM engine (100) thus allows for the benefits of both RAM and CAM devices, such as speed, density, cost and intuitiveness, without their inherent drawbacks. Further, the CAM engine (100) implements various flexible memory storage configurations for the keys and associations stored in RAM. Also, the CAM engine (100) implements certain algorithms that provide for the hashing of data, for table load and unload capabilities, for proximity matching, for dealing with overflow conditions, and for implementing hierarchical search capabilities.
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公开(公告)号：EP0644553B1
公开(公告)日：2000-07-12
申请号：EP94114546.8
申请日：1994-09-15
申请人： CODEX CORPORATION
CPC分类号： G11C15/04
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