WAREHOUSE AND FINE GRANULARITY SCHEDULING FOR SYSTEM ON CHIP (SOC)
    1.
    发明公开
    WAREHOUSE AND FINE GRANULARITY SCHEDULING FOR SYSTEM ON CHIP (SOC) 审中-公开
    芯片系统的仓库和细粒度调度(SOC)

    公开(公告)号:EP3308290A1

    公开(公告)日:2018-04-18

    申请号:EP16823901.0

    申请日:2016-07-14

    IPC分类号: G06F17/00

    摘要: A data warehouse includes a memory and a controller disposed on a substrate that is associated with a System on Chip (SoC). The controller is operatively coupled to the memory. The controller is configured to receive data from a first intellectual property (IP) block executing on the SoC; store the data in the memory on the substrate; and in response to a trigger condition, output at least a portion of the stored data to the SoC for use by a second IP block. An organization scheme for the stored data in the memory is abstracted with respect to the first and second IP blocks.

    TCAM-BASED TABLE QUERY PROCESSING METHOD AND APPARATUS
    2.
    发明公开
    TCAM-BASED TABLE QUERY PROCESSING METHOD AND APPARATUS 有权
    基于TCAM的表格查询处理方法和装置

    公开(公告)号:EP3012747A1

    公开(公告)日:2016-04-27

    申请号:EP14814274.8

    申请日:2014-04-21

    申请人: ZTE Corporation

    发明人: GU, Xia ZHANG, Qishen

    IPC分类号: G06F17/30

    摘要: Provided are a TCAM-based table query processing method and apparatus. The method includes: executing a first query process for querying a TCAM entry; while the first query process is executed, executing a second query process for querying one or more entries other than the TCAM entry, wherein the first query process and the second query process run independently of each other; and respectively acquiring a first query result and a second query result through the first query process and the second query process. The technical solution solves the technical problem in the related technologies that the packet processing time is long due to the TCAM-based table query manner and the packet forwarding performance is affected accordingly, shortens the packet processing time and improves the packet forwarding performance.

    摘要翻译: 提供了一种基于TCAM的表查询处理方法和装置。 该方法包括:执行查询TCAM表项的第一查询过程; 当执行所述第一查询过程时,执行用于查询除所述TCAM条目之外的一个或多个条目的第二查询过程,其中所述第一查询过程和所述第二查询过程彼此独立地运行; 并通过第一查询过程和第二查询过程分别获取第一查询结果和第二查询结果。 该技术方案解决了相关技术中由于基于TCAM的查表方式造成报文处理时间长,从而影响报文转发性能,缩短报文处理时间,提高报文转发性能的技术问题。

    SEARCH INFRASTRUCTURE
    3.
    发明公开
    SEARCH INFRASTRUCTURE 有权
    搜索基础结构

    公开(公告)号:EP2885731A4

    公开(公告)日:2016-04-20

    申请号:EP13829589

    申请日:2013-08-16

    申请人: TWITTER INC

    IPC分类号: G06F17/30

    摘要: A system for real-time search, including: a set of partitions, each including a set of segments, each segment corresponding to a time slice of messages posted to the messaging platform, and a real-time search engine configured to receive a search term in parallel with other partitions in the set of partitions, and search at least one of the set of segments in reverse chronological order of the corresponding time slice to identify document identifiers of messages containing the search term; and a search fanout module configured to: receive a search query including the search term; send the search term to each of the set of partitions for parallel searching; and return, in response to the search query, at least one of the identified document identifiers of messages containing the search term.

    PROCESSOR AND DATA GATHERING METHOD
    4.
    发明公开
    PROCESSOR AND DATA GATHERING METHOD 审中-公开
    PROZESSOR UND DATENERFASSUNGSVERFAHREN

    公开(公告)号:EP2950202A1

    公开(公告)日:2015-12-02

    申请号:EP15167062.7

    申请日:2015-05-11

    发明人: Kimura, Masayuki

    IPC分类号: G06F9/38 G06F9/312 G06F9/30

    摘要: An object of the present invention is to efficiently perform a data load process or a data store process between a memory and a storage unit in a processor. The processor includes: a plurality of storage units associated with a plurality of data elements included in a data set; and a control unit that reads the plurality of data elements stored in adjacent storage areas from a memory, in which a plurality of the data sets is stored, collectively for respective data sets, sorts the respective read data elements to a storage unit corresponding to the data element among the plurality of storage units, and writes the data elements to the respective data sets.

    摘要翻译: 本发明的目的是在处理器中有效地执行存储器和存储单元之间的数据加载处理或数据存储处理。 所述处理器包括:与包括在数据集中的多个数据元素相关联的多个存储单元; 以及控制单元,从存储有多个数据集的存储器中存储的相邻存储区域中的多个数据元素共同地读取用于各个数据集的控制单元,将各个读取数据元素分类到对应于 数据元素,并将数据元素写入各个数据集。

    SMART CACHE AND SMART TERMINAL
    5.
    发明公开
    SMART CACHE AND SMART TERMINAL 有权
    智能缓冲存储区和智能终端

    公开(公告)号:EP2808783A4

    公开(公告)日:2015-09-16

    申请号:EP12867234

    申请日:2012-06-29

    申请人: ZTE CORP

    IPC分类号: G06F9/44 G06F12/08

    摘要: The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define and reconfiguration unit configured to define a memory as a required cache memory according to the configuration information; a control unit, configured to control writing and reading of the cache memory and monitor instructions and data streams in real time; a memory unit, composed of a number of memory modules and configured to cache data; the required cache memory is formed by memory modules according to the definition of the software define and reconfiguration unit; and an intelligence processing unit, configured to process input and output data and transfer, convert and operate on data among multiple structures defined in the control unit. The disclosure can realize an efficient memory system according to the operating status of software, the features of tasks to be executed and the features of data structures through the flexible organization and management by the control unit and the close cooperation of the intelligence processing unit.

    Associative memory technology in intelligence analysis and course of action development
    6.
    发明公开
    Associative memory technology in intelligence analysis and course of action development 审中-公开
    联想记忆技术在情报分析和行动发展中的作用

    公开(公告)号:EP2573693A2

    公开(公告)日:2013-03-27

    申请号:EP12185215.6

    申请日:2012-09-20

    IPC分类号: G06F17/30

    CPC分类号: G06F17/30861 G06F17/30982

    摘要: A system (100) for analyzing unstructured data. The system includes an associative memory (102) including a plurality of data (104) in associated units having a plurality of associations. The associative memory (102) is configured to be queried based on at least one relationship selected from the group that includes direct relationships (114) and indirect relationships (116) among the plurality of data (104). The associative memory (102) further includes a content-addressable structure (118). The system also includes an analyzer (122) in communication with the associative memory (102), wherein the analyzer (122) is configured to parse and arrange the plurality of data (104) into comparable units (124, 126, 128) in response to a query (120). The analyzer (122) is configured to establish an ordered list (130) ranking the comparable units (124, 126, 128) in an order of precedence based on the query (120). ( Fig. 1 )

    摘要翻译: 一种用于分析非结构化数据的系统(100)。 该系统包括在具有多个关联的关联单元中包括多个数据(104)的关联存储器(102)。 关联存储器(102)被配置为基于从包括多个数据(104)之中的直接关系(114)和间接关系(116)的组中选择的至少一个关系来被查询。 关联存储器(102)还包括内容可寻址结构(118)。 该系统还包括与关联存储器(102)通信的分析器(122),其中分析器(122)被配置成响应于解析并将多个数据(104)布置成可比较的单元(124,126,128) 到查询(120)。 分析器(122)被配置为建立基于查询(120)以优先顺序对可比单元(124,126,128)进行排序的有序列表(130)。 (图。1)

    System for updating an associative memory
    7.
    发明公开
    System for updating an associative memory 有权
    系统zur Aktualisierung eines assoziativen Speichers

    公开(公告)号:EP2551854A1

    公开(公告)日:2013-01-30

    申请号:EP12177203.2

    申请日:2012-07-20

    IPC分类号: G11C15/00

    CPC分类号: G11C15/00 G06F17/30982

    摘要: A system (100) includes an associative memory (102), a first table (134), a second table (136), a comparator (164), and an updater (166). The associative memory (102) may include data and associations among data and may be built from the first table (134). The first table (134) may include a record (144) with a first and second field (150, 152). The associative memory may be configured to ingest the first field (150) and avoid ingesting the second field (152). The second table (136) may include a record (160) with a third field (162) storing information indicating whether the first field (150) has been ingested by the associative memory (102) or has been forgotten by the associative memory (102). The comparator (164) may be configured to compare the first and second table (134, 136) to identify one of whether the first field (150) should be forgotten or ingested by the associative memory (102). The updater (166) may be configured to update the associative memory (102) by performing one of ingesting or forgetting the first field (150).

    摘要翻译: 系统(100)包括关联存储器(102),第一表(134),第二表(136),比较器(164)和更新器(166)。 关联存储器(102)可以包括数据之间的数据和关联,并且可以从第一表(134)构建。 第一表(134)可以包括具有第一和第二场(150,152)的记录(144)。 关联存储器可以被配置为摄取第一场(150)并避免摄取第二场(152)。 第二表(136)可以包括具有第三字段(162)的记录(160),该第三字段(162)存储指示第一字段(150)是否已经被关联存储器(102)摄取或被关联存储器(102 )。 比较器(164)可以被配置为比较第一和第二表(134,136)以识别第一场(150)是否应被关联存储器(102)遗忘或摄取之一。 更新器(166)可以被配置为通过执行摄取或遗忘第一场(150)来更新关联存储器(102)。

    CONTENT ADDRESSED MEMORIES
    10.
    发明公开
    CONTENT ADDRESSED MEMORIES 有权
    内容所涉及的内容

    公开(公告)号:EP1155415A1

    公开(公告)日:2001-11-21

    申请号:EP99934849.3

    申请日:1999-07-15

    IPC分类号: G11C15/04

    CPC分类号: G06F17/30982 G11C15/04

    摘要: A content addressable memory comprises a CAM control logic unit (11) and a plurality of cells (10) connected in a chain. Each cell comprises a memory block (12) coupled to a common address bus (ADD), a comparator (14) coupled to a common data bus (DATA) and to the data interface of the memory block (12), switching means (15) coupling the data interface of the memory block with the data bus, and a logic block (13) including a Match flip-flop (16). The memory is operable in two phases, a Search phase and an Access phase. In the Search phase, a sequence of words on the common data bus (DATA) is serially matched with the contents of a sequence of addresses in the memory blocks (12) of the cells (10). In the Access phase, the cells matched in the Search phase are made serially available for access via the common address and data buses (ADD and DATA).

    摘要翻译: 内容可寻址存储器包括CAM控制逻辑单元(11)和以链条连接的多个单元(10)。 每个单元包括耦合到公共地址总线(ADD)的存储器块(12),耦合到公共数据总线(DATA)和存储器块(12)的数据接口的比较器(14),开关装置 )将存储器块的数据接口与数据总线耦合,以及包括匹配触发器(16)的逻辑块(13)。 内存可以分两个阶段进行操作,即搜索阶段和访问阶段。 在搜索阶段,公共数据总线(DATA)上的字序列与单元(10)的存储块(12)中的地址序列的内容串行匹配。 在访问阶段,在搜索阶段匹配的单元通过公共地址和数据总线(ADD和DATA)可串行访问。