公开(公告)号：EP1274182A4

公开(公告)日：2004-07-14

申请号：EP01917762

申请日：2001-03-30

申请人： SANYO ELECTRIC CO

发明人： DOI YOSHIHARU ,  ITOU TADAYOSHI

IPC分类号： H01Q3/26 ,  H04B7/08 ,  H04B7/10 ,  H04B7/26 ,  H04J3/00 ,  H04L7/00 ,  H04L27/14

CPC分类号： H04B7/0848 ,  H04B7/0851

摘要： Frequency and timing estimating units (57,58) measure frequency and timing offsets, respectively, from a signal received from a mobile station via a control channel. When a new radio connection to the mobile station is effected by setting upper an antenna directivity thereto, a weight calculating unit (53) uses the measured frequency and timing offsets to correct signals received via a communication channel. The signal from the mobile station is accurately separated from the corrected received signals.

公开(公告)号：EP0844764B1

公开(公告)日：2003-04-23

申请号：EP97119713.2

申请日：1997-11-11

申请人： NEC CORPORATION

发明人： Uda, Yoshihide

IPC分类号： H04L27/22 ,  H04L27/14 ,  H04L1/06

CPC分类号： H03J7/04 ,  H03J1/0083 ,  H04L1/06

公开(公告)号：EP0883951A4

公开(公告)日：2001-12-19

申请号：EP96925573

申请日：1996-07-29

申请人： ROCKWELL INTERNAT

发明人： LIPOWSKI JOSEPH T ,  PETRANOVICH JAMES E

IPC分类号： H04L27/14 ,  H03J3/08 ,  H03J7/04 ,  H04B1/10 ,  H04B1/16 ,  H04B1/26 ,  H04L27/06

CPC分类号： H03J3/08 ,  H03J7/04 ,  H04W52/0283 ,  Y02D70/00

摘要： The present invention relates to circuitry for a receiver having a low cost filter using automatic alignment of the center frequency of signals input to the filter to suppress noise and out-of-band signals from the filter output over a narrow bandwidth. An RF input signal to the receiver is downconverted to an IF frequency using a VCO, and the IF signal is provided to the low cost filter. The output of the filter is input to a frequency correction circuit and a distortion detection circuit. The distortion detection circuit provides an error signal including positive frequency shift errors determined from digital ones identified from the filter output signal, and negative frequency shift error signals determined from digital zeros in the filter output signal. The distortion detection circuit output is then provided through an infinite impulse response filter which integrates the distortion detection output to provide a voltage control signal to a voltage control input of the VCO and the frequency correction circuit. The VCO then automatically centers the frequency of the signal input to the low cost filter to suppress noise and out-of-band signals, and the frequency correction circuit removes error correction frequency shift provided by the VCO after downconversion. For battery powered devices, the infinite impulse response filter can maintain the state of the voltage control signal provided to the VCO upon receipt of a sleep mode signal after the sleep mode signal is disabled.\!

摘要翻译： 本发明涉及一种具有低成本滤波器的接收机的电路，其使用输入到滤波器的信号的中心频率的自动对准来在窄带宽上抑制来自滤波器输出的噪声和带外信号。 使用VCO将接收机的RF输入信号下变频到IF频率，并将IF信号提供给低成本滤波器。 滤波器的输出被输入到频率校正电路和失真检测电路。 失真检测电路提供包括从滤波器输出信号识别的数字确定的正频移误差的误差信号和滤波器输出信号中从数字零点确定的负频移误差信号。 然后通过无限脉冲响应滤波器提供失真检测电路输出，该无限脉冲响应滤波器对失真检测输出进行积分，以向VCO的电压控制输入端和频率校正电路提供电压控制信号。 VCO然后自动将信号输入的频率中心到低成本滤波器以抑制噪声和带外信号，并且频率校正电路去除下变频后由VCO提供的纠错频移。 对于电池供电的设备，无限脉冲响应滤波器可以在睡眠模式信号被禁用后接收到睡眠模式信号时保持提供给VCO的电压控制信号的状态。

公开(公告)号：EP1130863A2

公开(公告)日：2001-09-05

申请号：EP01301398.2

申请日：2001-02-19

申请人： LUCENT TECHNOLOGIES INC.

发明人： Leonard, Eric David ,  Subramanian, Suresh ,  Thomson, David J.

IPC分类号： H04L27/14 ,  H04L25/06 ,  H04L7/04

CPC分类号： H04L25/067 ,  H04L7/027 ,  H04L7/046 ,  H04L27/14

摘要： A method and apparatus are provided for use in a transceiver of a wireless system that enable analog mode operations to be performed using in-phase (I) and quadrature (Q) values. When operating in the analog mode, the apparatus comprises a processor that receives digital I, Q pairs relating to audio or data signals and performs FM demodulation to generate information content relating to the audio or data signals. When receiving data in the analog mode, the data is in a particular format. In order to decode the data, the processor looks at each bit of the data for five repeats of Radio Link Words (RLWs) and generates and stores a confidence factor associated with each bit. The confidence factor is based on how closely the waveform represents a 1 or a 0 as well as the signal strength. If the waveform has relatively little noise and if the RF signal strength is relatively high, the processor assigns more weight to its determination as to whether the waveform represents a 1 or a 0. Once this process has been performed for each repeat of the current RLW, the processor takes the sum of the confidence factors associated with each bit and compares the sum to a threshold level to determine whether the bit is a 1 or a 0. A signaling tone detection routine is utilized to distinguish between when data is being received and when signaling tone is being received.

摘要翻译： 提供了一种在无线系统的收发器中使用的方法和装置，其使得能够使用同相（I）和正交（Q）值来执行模拟模式操作。 当在模拟模式下操作时，该装置包括处理器，其接收与音频或数据信号相关的数字I，Q对，并执行FM解调以产生与音频或数据信号相关的信息内容。 当以模拟模式接收数据时，数据是特定的格式。 为了对数据进行解码，处理器查看五个重复的无线电链接字（RLW）的数据的每一位，并产生并存储与每个位相关联的置信因子。 置信因子是基于波形如何接近1或0以及信号强度。 如果波形具有相对较小的噪声，并且如果RF信号强度相对较高，则处理器对其波形是否表示1或0的确定赋予更多的权重。对于当前RLW的每次重复执行该处理 处理器获取与每个位相关联的置信因子之和，并将该和与门限电平进行比较，以确定该位是1还是0。使用信令音检测程序来区分正在接收数据的时间和 当正在接收信令音时。

公开(公告)号：EP0900490A4

公开(公告)日：2001-07-04

申请号：EP97924728

申请日：1997-05-20

申请人： MOTOROLA INC

发明人： CHEN WEIZHONG ,  DEHNER LEO G ,  CARSELLO STEPHEN ROCCO

IPC分类号： H04L1/16 ,  H04L7/027 ,  H04L7/04 ,  H04L27/00 ,  H04L27/148 ,  H04L27/233 ,  H04L27/38 ,  H03D3/00 ,  H03D3/24 ,  H04L27/06 ,  H04L27/14 ,  H04L27/16 ,  H04L27/22

CPC分类号： H04L27/2332 ,  H04L1/16 ,  H04L7/027 ,  H04L7/042 ,  H04L7/046 ,  H04L27/148 ,  H04L27/3854 ,  H04L2027/003 ,  H04L2027/0046 ,  H04L2027/0093

摘要： A receiver (109) and a method therein arranged and constructed to receive a signal using a noncoherent matched filter structure including a frequency detector (205) arranged to process a first portion (602) of the signal to provide a frequency error; a timing detector (206), responsive to the frequency error, arranged to process a second portion (604) of the signal to provide a timing error; and a symbol detector (209), responsive to the frequency error and the timing error, arranged to process a symbol portion (606) of the signal to provide a detected symbol.

公开(公告)号：EP1066675A1

公开(公告)日：2001-01-10

申请号：EP99910368.2

申请日：1999-03-19

申请人： TELEFONAKTIEBOLAGET LM ERICSSON

发明人： MATTISSON, Sven ,  HAARTSEN, Jacobus

IPC分类号： H03D3/00 ,  H04L27/14

CPC分类号： H03D3/005 ,  H04L27/152

摘要： A demoludator circuit for demoludating a frequency modulated input signal comprises filter means (10) and detector means (14) for receiving a frequency modulated input signal and for providing a demoludated output signal, tuning means (19) for tuning the frequency characterictics of the filter means and of the detector means, and DC offset estimator means (18) wich are operable to estim ate the DC offset of the demoludated output signal, and to produce an offset signal representing the estimated DC offset, and to provide the offset signal to the tuning means. The tuning means are operable to tune the frequency characteristics of the filter means and detector means in dependence upon the offset signal.

公开(公告)号：EP0815676A4

公开(公告)日：2000-07-05

申请号：EP96909641

申请日：1996-03-15

申请人： SARNOFF CORP

发明人： STROLLE CHRISTOPHER HUGH ,  JAFFE STEVEN TODD ,  LYONS PAUL WALLACE

IPC分类号： H04L27/38 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04N21/242 ,  H04N21/43 ,  H04N21/438 ,  H04L27/06 ,  H03K9/00 ,  H04L27/14 ,  H04L27/22 ,  H04N5/00 ,  H04N5/44 ,  H04N7/24 ,  H04N7/62

CPC分类号： H04L7/0029 ,  H04L7/0278 ,  H04N21/242 ,  H04N21/4302 ,  H04N21/4382 ,  H04N21/4384

摘要： A digital information receiver (100) having a single oscillator (118) providing a clock signal to the receiver circuitry. The receiver (100) contains, in addition to the oscillator (118), an input signal processor (102), a symbol time loop, a demodulator (106), a transport decoder (108), a transport timing loop, one or more applications decoders (102) and a presentation device (116). The input signal processor (102) digitizes an input signal and resamples the input signal using an interpolator (204) such that the input signal is optimally sampled. The resampling is controlled by a symbol timing loop. In a first embodiment, the transport timing loop controls the frequency of the oscillator (118) using transmitter timing information contained in the received signal. In the second embodiment, the oscillator (1202) is a free running oscillator and the transport timing loop controls a numerically controlled counter (1002) that, in turn, controls presentation timing of the information carried by the information in the input signal. After the input signal is decoded, an output interpolator (1204) generates continuous signals from somewhat bursty signals for utilization by the presentation device.

公开(公告)号：EP0670093B1

公开(公告)日：1999-01-13

申请号：EP93923619.6

申请日：1993-10-25

申请人： FORD MOTOR COMPANY

发明人： KENNEDY, John, Francis ,  PLOWDREY, Robert, Donald

IPC分类号： H04L27/14 ,  H03D3/02 ,  H03H7/19

CPC分类号： H04L27/1563

摘要： In an FSK demodulator, the received, modulated signal (A) is divided between two paths. In one path, the signal (A) undergoes non-linear amplification (11, 15), providing an amplitude limited output (C). In the other path, the signal (A) also undergoes non-linear amplification (10, 13), but, in addition, is subjected to a phase shift (12). The phase shift is positive at the frequency representing binary ones, and negative at the frequency representing binary zeros (or vice versa). Thus, the signal (B) from this second branch, is a phase shifted version of the signal (C) from the first. A phase detector (14), comprising a D type flip flop, provides the demodulated output.

摘要翻译： 在FSK解调器中，接收到的调制信号（A）在两个路径之间分配。 在一条路径中，信号（A）经历非线性放大（11,15），提供幅度限制输出（C）。 在另一路径中，信号（A）也经历非线性放大（10,13），但是另外经受相移（12）。 在代表二进制频率的频率处相移是正的，在代表二进制零的频率处相位是负的（反之亦然）。 因此，来自该第二分支的信号（B）是来自第一分支的信号（C）的相移版本。 包括D型触发器的相位检测器（14）提供解调输出。

公开(公告)号：EP0741478A3

公开(公告)日：1998-09-02

申请号：EP96106733

申请日：1996-04-29

申请人： MOTOROLA INC

发明人： CORLETTO JOSE G ,  KODRA GREGG S

IPC分类号： H03D1/00 ,  H03D3/00 ,  H03D3/06 ,  H03D5/00 ,  H04L27/152 ,  H04L27/227 ,  H04L27/38 ,  H04L27/14

CPC分类号： H04L27/2273 ,  H03D3/007 ,  H04L27/1525 ,  H04L27/3818

摘要： A circuit (10) for determining a radius value and a phase value from an in-phase signal I(n) and a quadrature signal Q(n) iteratively approximates the phase value and the radius value based upon initial in-phase signal and quadrature signal preferably using the CORDIC algorithm. The circuit (10) includes a multi-task arithmetic unit (50), memory (20), and a controller (30). The multi-task arithmetic unit includes registers (12, 14, 16), multiplexers (18, 22), shift registers (24, 25), and an adder (26) to perform various arithmetic operations. The circuit (10) further includes dynamic memory (32) for storing the solutions at different points in time of the radius value and phase value, which are subsequently used in the filtering of radius values and phase values.

公开(公告)号：EP0683586A3

公开(公告)日：1995-12-27

申请号：EP95107807.0

申请日：1995-05-22

申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

发明人： Schuermann, Josef ,  Hagl, Andreas

IPC分类号： H04L27/14

CPC分类号： H04L27/1563 ,  H04L27/142

摘要： An object of the invention in to provide a low-cost FSK receiver which self-calibrates itself such that demodulation of the FSK data stream is performed significantly are reliably with the least amount of additional cost and components. The reference setting for the comparator in the demodulator, which distinguishes between two different D.C. levels to yield either a high or low bit, is derived from the same oscillator that is used to generate the exciter signal. In addition, the generated reference setting signal is subjected to the same FSK signal processing chain as the IF frequencies described above, in order to provide a DC reference equivalent to the mid-FSK frequency. This results in a drift-free and stable reference input to the comparator which levels itself for integration, not requiring any level adjustment or trimming and adjusts for aging and drift.