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    Two port random access memory with column redundancy
    65.
    发明公开
    Two port random access memory with column redundancy 失效
    带有列冗余的两端口随机存取存储器

    公开(公告)号：EP0243859A2

    公开(公告)日：1987-11-04

    申请号：EP87105870.7

    申请日：1987-04-22

    申请人： International Business Machines Corporation

    发明人： Gray, Kenneth Stewart ,  Herrman, Bradley Donald

    IPC分类号： G06F11/20

    CPC分类号： G11C29/818 ,  G11C29/846 ,  G11C29/86

    摘要： A memory system includes a data storage matrix (11) having columns and rows and a redundant storage matrix having at least one column. The columns of the storage matrix are addressed by column addresses (B0-B7) each defining a logical column address for a data bit of a row and corresponding to a predetermined physical column of the storage matrix. The storage matrix is readable in parallel, the parallel read data being serially presented to an output port in a se­quence determined by the physical order of the columns of the storage matrix. Column redundancy logic, response to a column address corresponding to a defec­tive physical column of the storage matrix, stores a data bit in a column of the redundant storage matrix (31). Redundancy control logic (25, 30, 32, 33, 34) response to the column redundancy logic operates on data parallel read from the storage matrix by column addressing, to insert the data bit stored in the re­dundant column between the data bits read from the data storage matrix according to its logical column address.

    摘要翻译： 一种存储器系统包括具有列和行的数据存储矩阵（11）以及具有至少一列的冗余存储矩阵。 存储矩阵的列由列地址（B0-B7）寻址，每个列地址定义一行的数据位的逻辑列地址并且对应于存储矩阵的预定物理列。 存储矩阵可并行读取，并行读取数据以由存储矩阵的列的物理顺序确定的顺序串行地呈现给输出端口。 列冗余逻辑，响应与存储矩阵的缺陷物理列对应的列地址，将数据比特存储在冗余存储矩阵（31）的列中。 响应于列冗余逻辑的冗余控制逻辑（25,30,32,33,34）对通过列寻址从存储矩阵并行读取的数据进行操作，以将存储在冗余列中的数据位插入从 数据存储矩阵根据其逻辑列地址。