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    Repairable matrix display
    5.
    发明公开
    Repairable matrix display 失效
    Reparierbare Matrixanzeige。

    公开(公告)号：EP0601650A1

    公开(公告)日：1994-06-15

    申请号：EP93203396.2

    申请日：1993-12-03

    Applicant: Philips Electronics N.V.

    Inventor： Carlson, Allan

    IPC: G09G3/36 ,  G06F11/20

    CPC classification number: G11C29/86 ,  G09G3/3677 ,  G09G2330/08

    Abstract: A matrix display apparatus includes an addressing circuit for addressing pixels of the display by means of row-address conductors. The addressing circuit includes a shift register having successive stages coupled to the pixels through respective buffer devices which are electrically connected in the row-address conductors. In order to circumvent defects which would prevent a timing pulse from propagating through individual stages of the shift register, a number of spare shift-register stages are distributed along the length of the shift register. The spare stages can be connected in place of defective stages of the shift register via a pair of reparative conductors which insulatively cross the row-address conductors. Spare buffer devices are similarly provided.

    Abstract translation: 矩阵显示装置包括用于通过行地址导体寻址显示器的像素的寻址电路。 寻址电路包括移位寄存器，其具有通过电连接在行地址导体中的各个缓冲器件耦合到像素的连续级。 为了规避防止定时脉冲传播到移位寄存器的各个级的缺陷，沿着移位寄存器的长度分布了多个备用移位寄存器级。 备用级可以通过绝对地穿过行地址导体的一对修复导体来连接移位寄存器的缺陷级。 备用缓冲装置也同样提供。

    PROCEDE DE TEST POUR LES REGISTRES A DECALAGE REDONDANTS
    6.
    发明公开
    PROCEDE DE TEST POUR LES REGISTRES A DECALAGE REDONDANTS 失效
    试验方法用于冗余移位寄存器。

    公开(公告)号：EP0573550A1

    公开(公告)日：1993-12-15

    申请号：EP92907194.0

    申请日：1992-02-28

    Applicant: THOMSON-LCD

    Inventor： PLUS, Dora ,  DUPONT, Antoine, Pierre

    IPC: G06F11 ,  G11C29

    CPC classification number: G11C29/86 ,  G06F11/2221 ,  G11C29/003

    Abstract: Dispositif d'affichage avec une pluralité de lignes de sélection incluant des balayeurs redondants de lignes de sélection. Chaque balayeur inclut une pluralité d'étages équivalents dotés d'une borne d'entrée et d'une borne de sortie. Les étages et les lignes de sélection sont numérotés dans l'ordre et les étages de numéros correspondants sont connectés aux extrémités opposées des lignes de sélection de numéros correspondants par des segments de ligne séparée. Les étages dans chaque balayeur sont mis en cascade par connexion de la borne de sortie de chaque étage à la borne d'entrée de l'étage suivant immédiatement. Les balayeurs de lignes de sélection peuvent fonctionner indépendamment par la fourniture d'alimentations électriques et de générateurs de signaux d'horloge séparés. Pendant le test, on fait paraître l'un des balayeurs comme une impédance élevée vis-à-vis du balayeur en cours de test. Les étages défectueux d'un balayeur sont remplacés par l'étage de muméro correspondant de l'autre balayeur en coupant simplement le segment de ligne séparée de l'étage défectueux.

    Two port random access memory with column redundancy
    7.
    发明公开
    Two port random access memory with column redundancy 失效
    双端口随机存取存储器，带有冗余冗余

    公开(公告)号：EP0243859A3

    公开(公告)日：1990-03-21

    申请号：EP87105870.7

    申请日：1987-04-22

    Applicant: International Business Machines Corporation

    Inventor： Gray, Kenneth Stewart ,  Herrman, Bradley Donald

    IPC: G06F11/20

    CPC classification number: G11C29/818 ,  G11C29/846 ,  G11C29/86

    Abstract: A memory system includes a data storage matrix (11) having columns and rows and a redundant storage matrix having at least one column. The columns of the storage matrix are addressed by column addresses (B0-B7) each defining a logical column address for a data bit of a row and corresponding to a predetermined physical column of the storage matrix. The storage matrix is readable in parallel, the parallel read data being serially presented to an output port in a se­quence determined by the physical order of the columns of the storage matrix. Column redundancy logic, response to a column address corresponding to a defec­tive physical column of the storage matrix, stores a data bit in a column of the redundant storage matrix (31). Redundancy control logic (25, 30, 32, 33, 34) response to the column redundancy logic operates on data parallel read from the storage matrix by column addressing, to insert the data bit stored in the re­dundant column between the data bits read from the data storage matrix according to its logical column address.

    Bubble memory device
    8.
    发明公开
    Bubble memory device 失效
    泡泡记忆装置

    公开(公告)号：EP0029304A3

    公开(公告)日：1981-10-07

    申请号：EP80303733

    申请日：1980-10-22

    Applicant: CONTROL DATA CORPORATION

    Inventor： Toth, Dolan Harold

    IPC: G11C19/08

    CPC classification number: G11C29/86 ,  G11C19/0875

    Abstract: A bubble memory device of the word organised, fault tolerant type comprises a number of bubble memory chips (12-26) equivalent in number to a given word size, a correction bit bubble memory chip (28), a Programmable Read Only Memory (74) responsive to input addresses for identifying defective bit locations in the bubble memory chips, an address register (70) providing addresses to the PROM (74) and a decoder (78) substituting, in reading and writing operations, correction bits from the correction bit bubble memory chip (28) for bits in any one of the bubble memory chips in response to output signals from the PROM (74) identifying a defective bit location.

    Abstract translation: 容易组合的气泡存储器件包括数量相当于给定字大小的多个气泡存储器芯片（12-26），校正位气泡存储器芯片（28），可编程只读存储器（74） ）响应于用于识别气泡存储器芯片中的有缺陷的位位置的输入地址，向PROM（74）提供地址的地址寄存器（70）和在读取和写入操作中从校正位 响应来自识别缺陷位位置的PROM（74）的输出信号，气泡存储器芯片（28）用于任何一个气泡存储器芯片中的位。

    SHIFT REGISTER UNIT, GATE LINE DRIVING APPARATUS AND DRIVING METHOD
    9.
    发明公开
    SHIFT REGISTER UNIT, GATE LINE DRIVING APPARATUS AND DRIVING METHOD 审中-公开

    公开(公告)号：EP3361472A1

    公开(公告)日：2018-08-15

    申请号：EP16852863.6

    申请日：2016-09-30

    Applicant: BOE Technology Group Co., Ltd. ,  Beijing BOE Display Technology Co., Ltd.

    Inventor： WANG, Zheng

    IPC: G09G3/36

    CPC classification number: G09G3/3685 ,  G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0286 ,  G11C7/1036 ,  G11C7/20 ,  G11C19/28 ,  G11C19/30 ,  G11C29/022 ,  G11C29/86

    Abstract: A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module (200) connected between an input terminal (INPUT) and a pull-up node (PU), and configured to charge the pull-up node (PU); an output module (205) connected between the pull-up node (PU), a first clock signal terminal (CK) and an output terminal (OUTPUT), and configured to output to the output terminal (OUTPUT) a first clock signal received at the first clock signal terminal (CK); a pull-up node reset module (215) connected between a reset terminal (RESET-IN), a pull-down node (PD) and the pull-up node (PU), and configured to reset the pull-up node (PU); and an output reset module (220) connected between a second clock signal terminal (CKB), the pull-down node (PD) and the output terminal (OUTPUT), and configured to reset the output terminal (OUTPUT). The shift register unit, a gate line driving device and a driving method can downsize an overall structure of the GOA, reduce power consumption, decrease signal delay, improve signal waveform, and also enhance reliability of the GOA circuit in entirety.

    Nonvolatile resistive memories, latch circuits, and operation circuits having scalable two-terminal nanotube switches
    10.
    发明公开
    Nonvolatile resistive memories, latch circuits, and operation circuits having scalable two-terminal nanotube switches 审中-公开
    非易失性阻变存储器，阻断与可扩展的纳米管开关电路和操作电路与两个端子

    公开(公告)号：EP2104109A1

    公开(公告)日：2009-09-23

    申请号：EP09159276.6

    申请日：2007-08-08

    Applicant: Nantero, Inc.

    Inventor： Bertin, Claude ,  Rueckes, Thomas ,  Ward, Jonathan ,  Guo, Frank ,  Konsek, Steven ,  Meinhold, Mitchell

    IPC: G11C11/00 ,  G11C13/02 ,  G11C11/56 ,  G11C11/14 ,  G11C29/00 ,  G11C17/16

    CPC classification number: H01L51/0587 ,  B82Y10/00 ,  G11C11/56 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/025 ,  G11C14/00 ,  G11C17/16 ,  G11C29/86 ,  G11C2013/0076 ,  G11C2213/19 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L51/0048

    Abstract: A non-volatile resistive memory is provided. The memory includes at least one non-volatile memory cell and selection circuitry. Each memory cell has a two-terminal nanotube switching device having and a nanotube fabric article disposed between and in electrical communication with conductive terminals. Selection circuitry is operable to select the two-terminal nanotube switching device for read and write operations. Write control circuitry, responsive to a control signal, supplies write signals to a selected memory cell to induce a change in the resistance of the nanotube fabric article, the resistance corresponding to an informational state of the memory cell. Resistance sensing circuitry in communication with a selected memory cell, senses the resistance of the nanotubc fabric article and provides the control signal to the write control circuitry. Read circuitry reads the corresponding informational state of the memory cell. A non-volatile latch circuit and a non-volatile register file configuration circuit for use with a plurality of non-volatile register files are also provided.

    Abstract translation: 本发明提供一种非易失性阻变存储器。 该存储器包括至少一个非易失性存储单元和选择电路。 每个存储单元具有两端子纳米管具有切换装置和之间并与导电端子电连通设置在纳米管的织物制品。 选择电路可操作用于选择读出用双端纳米管开关装置和写入操作。 写控制电路，响应于控制信号，供给写入信号到一个选择的存储单元以诱导纳米管织物制品，向存储单元的信息态对应的电阻的电阻值的变化。 电阻感测与所选择的存储单元的通信电路，感测所述织物制品nanotubc的电阻，并提供该控制信号到写入控制电路。 读取电路读取存储单元的相应信息的状态。 因此，提供一种非易失性锁存电路和用于与非易失性寄存器文件多元使用一个非易失性寄存器文件中的配置电路。

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