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    PROCEDE DE TELECOMMUNICATION ATM DANS LEQUEL DES TERMINAUX EMMETTENT VERS UNE MEME STATION
    66.
    发明公开
    PROCEDE DE TELECOMMUNICATION ATM DANS LEQUEL DES TERMINAUX EMMETTENT VERS UNE MEME STATION 有权
    连接了站正在为ATM电信终端设备的方法

    公开(公告)号：EP1142437A1

    公开(公告)日：2001-10-10

    申请号：EP99964519.5

    申请日：1999-11-24

    申请人： ALCATEL

    发明人： SEHIER, Philippe

    IPC分类号： H04Q11/04

    CPC分类号： H04J13/16 ,  H04B7/18582 ,  H04L2012/5607 ,  H04L2012/5608 ,  H04L2012/5673 ,  H04Q11/0478

    摘要： The invention concerns a method for transmitting digital signals in asynchronous mode whereby the terminals (16, 18) transmit to a common station (20). The communications are transmitted by cells (40, 42, 44, 46) and the terminals successively transmitting at separate periods (60, 62, 64, 66; 70, 72, 74), to each cell being assigned at least two orthogonal codes (C1, C2, C3, C4). The invention is characterised in that the duration of the period during which each terminal transmits, and/or the number of codes assigned to each terminal, and/or the number of symbols of one specific code assigned in a terminal can be selected at each transmission, according to the a specific power level (80).

    DETERMINING TIME SLOT DELAY FOR ATM TRANSMISSIONS
    67.
    发明公开
    DETERMINING TIME SLOT DELAY FOR ATM TRANSMISSIONS 审中-公开
    时隙的时滞ATM变速箱测定

    公开(公告)号：EP1114568A1

    公开(公告)日：2001-07-11

    申请号：EP99951334.4

    申请日：1999-09-17

    申请人： TELEFONAKTIEBOLAGET L M ERICSSON (publ)

    发明人： EKSTEDT, Ulf

    IPC分类号： H04Q11/04

    CPC分类号： H04Q11/0478 ,  H04L2012/5673 ,  H04L2012/5674

    摘要： A time slot aligner (60) determines delay (in terms of frames) of time slots of a set of frames received on Plesiochronous Digital Hierarchy (PHD) transmission network. In accordance with the time slot frame/delay determination technique of the invention, the time slot aligner finds an initial header of an ATM cell by searching five consecutive time slots in nearby frames of the set of frames. Once the initial header is found, a frame/delay value is determined for each time slot comprising the header. The frame/delay values for selected time slots of the header are then used to form a window which is used for searching for the next header. Searching for a next header for a next ATM cell involves sliding the window to other frames of the set of frames and searching for a value in a successive time slot which will form a HEC byte for a header framed by the sliding window. When a next header is located, a frame/delay determination has to be made only for the last time slot of the header, e.g., the time slot which formed the HEC byte. A new window is then formed using the frame/delay pattern from the most-recently acquired header, and that new window slid to find yet another header. Header location, time slot frame/delay determination, and formation of a new window continue until a frame/delay determination is made for all time slots of the set of frames.

    Frame synchronization method and frame synchronization circuit
    69.
    发明公开
    Frame synchronization method and frame synchronization circuit 审中-公开
    Verfahren und Schaltung zur Ra​​hmensynchronisation

    公开(公告)号：EP1051056A2

    公开(公告)日：2000-11-08

    申请号：EP00109529.8

    申请日：2000-05-04

    申请人： NEC CORPORATION

    发明人： Kameyama, Chihiro, NEC IC Microcomputer Syst., Ltd

    IPC分类号： H04Q11/04

    CPC分类号： H04Q11/0478 ,  H04L2012/5673 ,  H04L2012/5674

    摘要： A frame synchronization circuit allows the user to set up a backward protection stage count and a forward protection stage count to arbitrary values. The frame synchronization circuit has a frame synchronization pattern detecting circuit for detecting a frame synchronization pattern from received frame data and outputting a frame synchronization pattern detection signal, a frame synchronization state transition managing circuit for managing frame synchronization state transitions, and a frame timing generating circuit for detecting a transition from a hunting state managed by the frame synchronization state transition managing circuit and generating an enable signal. The frame synchronization state transition managing circuit manages the number of times that the frame synchronization pattern is detected and the number of times that the frame synchronization pattern is not detected, based on the enable signal and the frame synchronization pattern detection signal, makes a transition from the hunting state to a synchronization state if the frame synchronization pattern is detected consecutively for the backward protection stage count which is set up arbitrarily, and makes a transition from the synchronization state to the hunting state if the frame synchronization pattern is not detected consecutively for the forward protection stage count which is set up arbitrarily.

    摘要翻译： 帧同步电路允许用户将后向保护级计数和正向保护级数设置为任意值。 帧同步电路具有帧同步模式检测电路，用于从接收的帧数据检测帧同步模式并输出帧同步模式检测信号，用于管理帧同步状态转换的帧同步状态转换管理电路和帧定时发生电路 用于检测由帧同步状态转换管理电路管理的捕获状态的转换并产生使能信号。 帧同步状态转移管理电路基于使能信号和帧同步模式检测信号，管理检测到帧同步模式的次数和不检测帧同步模式的次数，从 如果对于任意设置的后向保护级计数连续检测到帧同步模式，则将寻呼状态转换到同步状态，并且如果没有连续检测到帧同步模式，则从同步状态向捕捉状态转变 前置保护阶段计数任意设定。

    CRYPTOGRAPHIC SYSTEM FOR PUBLIC ATM/SONET COMMUNICATION SYSTEM WITH VIRTUAL CIRCUIT LOOKUP
    70.
    发明公开
    CRYPTOGRAPHIC SYSTEM FOR PUBLIC ATM/SONET COMMUNICATION SYSTEM WITH VIRTUAL CIRCUIT LOOKUP 审中-公开
    加密系统与VC查找公用ATM / SONET通信系统

    公开(公告)号：EP1016310A1

    公开(公告)日：2000-07-05

    申请号：EP98950622.5

    申请日：1998-09-14

    申请人： Celotek Corporation

    发明人： WINKELSTEIN, Daniel, R. ,  STEVENSON, Daniel, S. ,  HILLERY, Nathan, H. ,  BYRD, Gregory, T.

    IPC分类号： H04Q11/04

    CPC分类号： H04Q11/0478 ,  H04L2012/5673 ,  H04L2012/5687

    摘要： A communications system employing sending and receiving cryptographic units provides transparent security for digital communications in Asynchronous Transfer Mode Networks. Each cryptographic unit is placed between the untrusted network and a secure host or LAN. The cryptographic unit replaces the cleartext packet with encrypted text, and manages all keys between sender and receiver so as to be transparent to the user. Plural virtual circuits, each with distinct cryptographic state information, are processed in real time. Packet cryptographic processing time is reduced by ordering a list of active virtual circuits and using a binary search to lookup cryptographic state information for each virtual circuit. In addition, triple DES encryption and decryption is implemented in a pipelined data flow architecture using multiple FIFO storage for algorithmic key agility permitting both triple and single DES operations using the same cryptographic unit.