公开(公告)号：EP1933458A1

公开(公告)日：2008-06-18

申请号：EP07291438.5

申请日：2007-11-30

申请人： IFP

发明人： Grouffal, Christian ,  Thierry, Gérard

IPC分类号： H03H17/00 ,  F02D41/02

CPC分类号： H03H17/0027 ,  F02D41/28 ,  F02D2041/1432 ,  F02D2041/285 ,  F02D2041/288

摘要： - Méthode de synchronisation d'un signal issu d'au moins un capteur positionné sur un moteur avec un évènement périodique du moteur, tel que la rotation du vilebrequin.
- On acquiert un signal de rotation vilebrequin indicatif d'un instant de référence (TR), sur lequel on souhaite synchroniser le ou les signaux moteur. On mesure l'écart de temps effectif (D) entre l'instant de référence et l'instant le plus proche de chaque signal moteur échantillonné temporellement. Puis, on détermine les coefficients d'un filtre numérique de compensation fractionnaire(FSDF) propre à compenser la partie fractionnaire (d) de l'écart de temps effectif mesuré. Enfin, on applique ce filtre numérique de compensation à chaque signal moteur échantillonné temporellement, permettant d'obtenir une série d'échantillons numérisés rééchelonnée depuis l'instant de référence (TR) pour chaque signal moteur.
- Application notamment au contrôle moteur.

摘要翻译： 该方法涉及通过在一组瞬时数字化和采样来自传感器的发动机信号来产生一系列样品。 获取表示基准时刻（TR）的同步信号。 测量该组瞬间中的基准时刻与最近时刻之间的有效时间差（D）。 计算分数数字滤波器的系数以补偿差值。 将样本应用于滤波器以获得即时（TR）的另一系列数字化和重组结构样本。 发动机基于后一系列样品进行控制。

公开(公告)号：EP1160976B1

公开(公告)日：2007-09-05

申请号：EP00981820.4

申请日：2000-12-18

申请人： SEIKO EPSON CORPORATION

发明人： KENMOCHI, Nobuhiko

IPC分类号： H03H17/00 ,  H04B1/707 ,  H03H17/02

CPC分类号： H04B1/7093 ,  G11C19/00

摘要： The number of passings of individual bits of input data through the shift register of a noncyclic digital filter is reduced to save electric power. Despread data is supplied to a 1st shift register (21) and a 2nd shift register (22) when the normal number of stages is divided into two, and both the shift registers are alternately made to perform shift operations at both the edges of a shift clock (CK). Multiplexers (MP11 - MP14) which select odd number codes among reference codes stored in a reference code register (23) while the shift clock (CK) is in an off-state and selects even number codes while the shift clock (CK) is in an on-state and multiplexers (MP21 - MP24) which select reversely are provided. The outputs of the exclusive ORs of the outputs of the respective stages of the 1st shift register (21) and the outputs of the multiplexers (MP11 - MP14) and the outputs of the exclusive ORs of the outputs of the respective stages of the 2nd shift register (22) and the outputs of the multiplexers (MP21 - MP24) are added to each other by an adder (25) to produce a correlation intensity output.

公开(公告)号：EP1367721A4

公开(公告)日：2005-11-02

申请号：EP02702727

申请日：2002-03-04

申请人： NEURO SOLUTION CORP

发明人： KOYANAGI YUKIO

IPC分类号： H03M1/66 ,  G06F1/02 ,  H03H17/00 ,  H03H17/06 ,  H03M1/00 ,  H03M3/04 ,  H03M3/02

CPC分类号： H03H17/0657 ,  G06F1/02 ,  H03M3/508

摘要： While a digital input is oversampled up to eight times to process and the oversample data into a specified digital fundamental waveform with multipliers/adders (4-10) to carry out only folding operation with delay circuits 11-1-11-4 and the multipliers/adders (12-15) to allow the determination of a continuous interpolating value. Thus, it is sufficient to provide no low-pass filter which causes a deterioration in phase characteristics. A limited number of determined interpolating functions are determined to prevent a truncation error in interpolation. An AND gate (2) is used to determine a part of the oversample data as the input data, so that processing and folding operation of digital fundamental waveform is carried out in a very simple processing.

公开(公告)号：EP1454261A4

公开(公告)日：2005-09-14

申请号：EP02805537

申请日：2002-12-04

申请人： LECROY CORP

发明人： GORBICS MARK STEVEN

IPC分类号： G01R13/00 ,  G06F17/17 ,  H03H17/00 ,  H03H17/06

CPC分类号： H03H17/0664 ,  G01R13/0272 ,  G06F17/17

摘要： A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.

摘要翻译： 抽取系统和抽取电路，用于在示波器上抽取波形数据。 抽取电路使用并联连接到数据总线的16个并行16对1多路复用器来实现，该数据总线基于由采样计数电路产生的控制信号选择性地采样采样。 可以输入抽取因子和相位值来编程电路执行的抽取量。 抽取系统在控制抽取时提供了更大的灵活性，并且通过将几个抽取电路与相应的模数转换器和存储器段相结合而形成。

公开(公告)号：EP1286619A4

公开(公告)日：2005-03-16

申请号：EP01946090

申请日：2001-06-05

申请人： MASIMO CORP

发明人： WEBER WALTER M ,  AL-ALI AMMAR

IPC分类号： A61B5/00 ,  A61B5/145 ,  A61B5/1455 ,  G06F17/00 ,  G06F17/18 ,  H03H17/00

CPC分类号： A61B5/7271 ,  A61B5/0002 ,  A61B5/021 ,  A61B5/1455 ,  A61B5/14551 ,  A61B5/6826 ,  A61B5/6829 ,  A61B5/6838 ,  A61B5/72 ,  A61B5/7207 ,  A61B5/7239 ,  G06K9/0051

摘要： A variable indication estimator which determines an output value representative of a set of input data. For example, the estimator can reduce input data to estimates of a desired signal, select a time, and determine an output value from the estimates and the time. In one embodiment, the time is selected using one or more adjustable signal confidence parameters determine where along the estimates the output value will be computed. By varying the parameters, the characteristics of the output value are variable. For example, when input signal confidence is low, the parameters are adjusted so that the output value is a smoothed representation of the input signal. When input signal confidence is high, the parameters are adjusted so that the output value has a faster and more accurate response to the input signal.

公开(公告)号：EP1125363A4

公开(公告)日：2004-04-07

申请号：EP99952917

申请日：1999-09-15

申请人： MOTOROLA INC

发明人： MCCOY JAMES WESLEY

IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H04B14/04 ,  H04L27/00

CPC分类号： H03H17/0685 ,  H03H17/0273 ,  H03H17/0275 ,  H03H2218/06

摘要： A multichannel polyphase filter (304, 602) includes a processing system (204, 506) for accepting and processing M input channels of data, each sampled at an input sampling rate, wherein M is a positive integer greater than unity. The processing system is programmed to provide a commutator (308, 606) for the multichannel polyphase filter, wherein the position of the commutator is decoupled from the phase of a filter impulse response selected for the position, thereby allowing the multichannel polyphase filter to be operated at a sampling rate that is a non-integer multiple of the input sampling rate. The processing system is further programmed to operate the multichannel polyphase filter at the non-integer multiple of the input sampling rate to obtain a non-integer sampling rate change.

公开(公告)号：EP1374399A1

公开(公告)日：2004-01-02

申请号：EP02718740.0

申请日：2002-03-28

申请人： Coding Technologies Sweden AB

发明人： EKSTRAND, Per

IPC分类号： H03H17/00

CPC分类号： H03H17/0266

摘要： The present invention proposes a new method and apparatus for the improvement of digital filterbanks, by a complex extension of cosine modulated digital filterbanks. The invention employs complex-exponential modulation of a low-pass prototype filter and a new method for optimizing the characteristics of this filter. The invention substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filterbank as an spectral equalizer. The invention is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The invention offers essential improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filterbanks used in high frequency reconstruction (HFR) systems.

公开(公告)号：EP0848535A3

公开(公告)日：2003-04-02

申请号：EP97309913.8

申请日：1997-12-09

申请人： Nokia Corporation

发明人： Carlsen, Sten

IPC分类号： H03H7/38 ,  H03H11/30 ,  H03H11/40 ,  H03H17/00 ,  H04M19/00

CPC分类号： H04M3/005

摘要： An interface unit for providing impedance matching with the impedance Z line between two transmission line terminals and a transmitter/receiver unit connected thereto comprises a current generator for generating an AC current running into the transmission line, a device for sensing the voltage across the two terminals of the transmission line, and a control device receiving a value of the sensed voltage and controlling the current generator in response thereto, so that said current generator supplies an AC current which, together with the voltage across the two terminals of the transmission line, ensures that, seen from the transmission line, the unit has an output impedance corresponding to the transmission line impedance Z line .

公开(公告)号：EP0750831A4

公开(公告)日：2003-02-05

申请号：EP95913600

申请日：1995-03-16

申请人： HEARING INNOVATIONS INC

发明人： DIABACHI FARID ,  RICHARDSON CHARLES S ,  LIPPA ARNOLD S

IPC分类号： G10L21/04 ,  H03H17/00 ,  H04R25/00

CPC分类号： H04R25/353 ,  H04R25/505

摘要： Apparatus and method for shifting the frequency range of an audio frequency range signal using digital frequency shifting and single sideband amplitude modulation techniques. In one embodiment, the audio signal (2) is shifted to an ultrasonic frequency range utilizing digital signal processing techniques in which an audio frequency signal is frequency shifted by modulation to a carrier frequency and in which a single sideband modulated signal (6) is formed.

公开(公告)号：EP1241784A1

公开(公告)日：2002-09-18

申请号：EP02075834.8

申请日：2002-03-04

申请人： Koninklijke Philips Electronics N.V.

发明人： Bedgedjian, Jean-Christophe

IPC分类号： H03H17/00 ,  H04L7/02

CPC分类号： H03H17/0642 ,  H03H17/0628 ,  H03H2218/08 ,  H04L7/0029 ,  H04L7/0091

摘要： La présente invention concerne un modulateur numérique (DM) et un procédé de modulation associé. Le modulateur numérique (DM) comporte une fréquence d'horloge (Fclk) et est apte à traiter un signal numérique (S(TA)) comprenant des symboles (SYMB) échantillonnés à une fréquence symbole (Fsy) Il se caractérise par des moyens d'interpolation (INT) aptes à interpoler un nouvel échantillon (OUT) à partir de paramètres d'interpolation (δ, SIGN) et de signaux (LS, TS, F0, F2) dérivés du signal numérique (S(TA)), des paramètres d'interpolation (δ, SIGN) étant calculés en fonction d'un ratio (R) variable et réel proportionnel à la fréquence symbole (Fsy) sur la fréquence d'horloge (Fclk).

摘要翻译： 数字调制器（DM）具有以符号频率（Fsy）处理包含采样符号（SYMB）的数字信号（S（TA））的时钟频率（Fclk）。 存在从内插参数和从数字信号输入得到的信号的内插器（INT）内插样本（OUT）。 根据时钟频率上与频率符号成比例的变量与实际因子的比率，计算插值参数。