摘要:
La présente invention concerne un modulateur numérique (DM) et un procédé de modulation associé. Le modulateur numérique (DM) comporte une fréquence d'horloge (Fclk) et est apte à traiter un signal numérique (S(TA)) comprenant des symboles (SYMB) échantillonnés à une fréquence symbole (Fsy) Il se caractérise par des moyens d'interpolation (INT) aptes à interpoler un nouvel échantillon (OUT) à partir de paramètres d'interpolation (δ, SIGN) et de signaux (LS, TS, F0, F2) dérivés du signal numérique (S(TA)), des paramètres d'interpolation (δ, SIGN) étant calculés en fonction d'un ratio (R) variable et réel proportionnel à la fréquence symbole (Fsy) sur la fréquence d'horloge (Fclk).
摘要:
The present application relates to an adaptive filter using manageable resource sharing and a method of operating the adaptive filter. The adaptive filter comprises a cluster controller configured for allocating each of several computational blocks to one of several clusters and a routing controller for configuring the routing of tapped delay signals by a routing logic to the respective cluster in accordance with an allocation of the tapped delay signals to the clusters. Each of computational blocks is configured for adjusting one filter coefficient, c i (n), in one cycle of an iterative procedure according to an adaptive convergence algorithm. The number of computational blocks is less than an order of the adaptive filter.
摘要:
A rake receiver where a shared moving average filter is operable in a multiplexed manner to receive and filter outputs from a plurality of pilot signal correlators.
摘要:
A multiplexed FIR/IIR digital filter structure (300) which offers linear phase response and low group delay by switching on a FIR filter portion (31) or a IIR filter portion (32). To reduce the silicon area, the FIR/IIR filter (300) shares registers which is enabled because the FIR and IIR processing do not use the registers at the same time but rather consecutively. Further, the multiplexed FIR/IIR digital filter structure (300) can offer limit-cycle-free IIR operation using two's-complement truncation in combination with positive valued allpass coefficients.
摘要:
La présente invention concerne un convertisseur de signal numérique d'entrée (1) en un signal numérique de sortie (3) à partir d'un ensemble de coefficients de filtrage. Le convertisseur comprend des moyens de filtrage réalisant une fonction de filtrage et fournissant l'ensemble de coefficients de filtrage à partir de déphasages (2) entre un échantillon du signal numérique de sortie et des échantillons du signal numérique d'entrée, la fonction de filtrage étant définie par un ensemble de polynômes. Les moyens de filtrage comprennent en outre une mémoire (52) pour stocker des coefficients des polynômes, et des moyens de calcul (53) de l'ensemble de coefficients de filtrage à partir des coefficients des polynômes et des déphasages. Un tel convertisseur permet un grand nombre de conversions de format, tout en disposant de ressources mémoire limitées.
摘要:
A filter device (403) and method for suppressing effects of Adjacent-Channel Interference of a received signal in a Frequency-Division-Multiple-Access system by filtering a baseband signal (s) of the received signal. The filter device (403) comprises an interference filter (4032), which is a complex digital Single-Input-Multiple-Output, SIMO, filter that is adapted to simultaneously generate a first signal (x) filtered at an upper-frequency-band and a second signal (y) filtered at a lower-frequency-band, wherein the first signal (x) is separate from the second signal (y). The filter device (403) also comprises a selector (4033) adapted to select one of the signals (s, x, y) as the output from the filter device (403).
摘要:
The invention calls for two multiplication units (M1i, M2i) to be included in each coefficient block (KBi) of n coefficient blocks, the multiplication units being used several times if the internal rate of the filter (F) is several times higher than the external rate required by the filter (F).