公开(公告)号：EP2474969A1

公开(公告)日：2012-07-11

申请号：EP11193980.7

申请日：2011-12-16

申请人： Samsung Mobile Display Co., Ltd.

发明人： Jang, Hwan-Soo ,  Pyon, Chang-Soo

IPC分类号： G09G3/32 ,  G11C19/28

CPC分类号： G09G3/3266 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2330/025 ,  G09G2330/027 ,  G11C19/184 ,  G11C19/28

摘要： An emission control line driver is capable of securing the stability of an output and of freely controlling the width of emission control signals. The emission control line driver includes a plurality of stages (321) respectively coupled to emission control lines (E1). Each of the stages includes a plurality of transistors (M1-M14) that are configured to output the emission control signal. The width of the emission control signal may be controlled to correspond to the width of a start signal. Furthermore, a circuit structure of the stages is simplified.

摘要翻译： 排放控制线驱动器能够确保输出的稳定性和自由地控制排放控制信号的宽度。 发射控制线驱动器包括分别耦合到发射控制线（E1）的多个级（321）。 每个级包括被配置为输出发射控制信号的多个晶体管（M1-M14）。 发射控制信号的宽度可以被控制以对应于起始信号的宽度。 此外，阶段的电路结构被简化。

公开(公告)号：EP2463853A1

公开(公告)日：2012-06-13

申请号：EP11739629.1

申请日：2011-01-20

申请人： Sony Corporation

发明人： TSUCHIDA, Yuji

IPC分类号： G09G5/36 ,  G09G3/20 ,  G09G5/00 ,  G09G5/38 ,  G09G5/391 ,  H04N13/04

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  H04N13/261

摘要： Provided are a mask addition unit for adding a mask to an input image of a two-dimensional (2D) image on the basis of a parameter for converting the 2D image into a three-dimensional (3D) image by a monocular stereopsis principle, a conversion unit for converting the input image to which the mask is added by the mask addition unit into a right-eye image and a left-eye image by the monocular stereopsis principle, and a display unit for displaying the right-eye image and the left-eye image.

摘要翻译： 提供了一种掩模添加单元，用于基于用于通过单目立体观察原理将2D图像转换为三维（3D）图像的参数将掩模添加到二维（2D）图像的输入图像， 转换单元，用于通过单眼立体原理将由掩模添加单元添加掩模的输入图像转换成右眼图像和左眼图像;以及显示单元，用于显示右眼图像和左眼图像 -ee图像。

公开(公告)号：EP2455931A1

公开(公告)日：2012-05-23

申请号：EP10799655.5

申请日：2010-02-17

申请人： Sharp Kabushiki Kaisha

发明人： SAKAMOTO, Mayuko ,  IWASE, Yasuaki

IPC分类号： G09G3/36 ,  G02F1/133 ,  G09G3/20

CPC分类号： G09G3/3677 ,  G02F1/13454 ,  G09G3/3266 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

摘要： A gate driver is provided with an odd-numbered stage shift register, an even-numbered stage shift register, and main lines including clock signal main lines. Each stage (bistable circuit) of one of the shift registers receives the first clock CKA and the second clock CKB from the clock signal main lines, and the third clock CKC and the fourth clock CKD from an adjacently provided stage of the other register (the odd-numbered stage shift register, if the stage is the even-numbered stage). Each stage of the shift register can receive the second clock CKB from a different stage of the same shift register. With this, it is possible to reduce a picture-frame area of a panel in a display device provided with a scanning signal line drive circuit having the plurality of shift registers.

摘要翻译： 栅极驱动器设置有奇数级移位寄存器，偶数级移位寄存器和包括时钟信号主线的主线。 一个移位寄存器的每个级（双稳态电路）从时钟信号主线接收第一时钟CKA和第二时钟CKB，并且从另一个寄存器的相邻提供级接收第三时钟CKC和第四时钟CKD 奇数级移位寄存器，如果级是偶数级）。 移位寄存器的每个级可以从相同移位寄存器的不同级接收第二时钟CKB。 由此，能够减少设置有具有多个移位寄存器的扫描信号线驱动电路的显示装置中的面板的画面区域。

公开(公告)号：EP2447950A1

公开(公告)日：2012-05-02

申请号：EP10791894.8

申请日：2010-03-01

申请人： Sharp Kabushiki Kaisha

发明人： OHHASHI, Seiji

IPC分类号： G11C19/28 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3275 ,  G09G3/3685 ,  G09G2310/0286 ,  G09G2320/0209 ,  G11C19/184

摘要： A display device is implemented that can suppress degradation in display quality caused by crosstalk, without causing an increase in frame size or an increase in power consumption. Each bistable circuit includes an output terminal (49) that outputs a state signal; a thin film transistor (T1) having a drain terminal to which a high-level potential (VDD) is provided, and a source terminal to which the output terminal (49) is connected; a thin film transistor (T2) having a source terminal connected to a region netA connected to a gate terminal of the thin film transistor (T1), and a gate terminal to which a clock (CKA) is provided; a thin film transistor (T6) for increasing the potential of a region netZ connected to a drain terminal of the thin film transistor (T2); and thin film transistors (T4, T5, and T3) for decreasing the potentials of the netA, the netC, and the output terminal (49), respectively. A channel area of the thin film transistor (T1) is larger than that of the thin film transistor (T2).

摘要翻译： 一种显示装置来实现并可以抑制由串扰引起的显示品质的降低，而不会导致在帧大小以增加或功耗增加。 每个双稳态电路包括输出端（49）没有输出的状态信号; 的薄膜晶体管（T1）具有一个漏极端子被提供一个高电平电位（VDD），和一个源端，其输出端（49）连接; 具有连接到内塔连接到该薄膜晶体管（T1）的栅极端子的区域中的源极端子，和栅极端子，其提供了一种时钟（CKA）的薄膜晶体管（T2）; 为增加NETZ连接到薄膜晶体管（T2）的漏极端子的区域的电位的薄膜晶体管（T6）; 和薄膜晶体管（T4，T5和T3）用于降低NETA，所述NETC，和输出端（49），分别的电位。 薄膜晶体管（T1）的一个信道面积比薄膜晶体管（T2）的直径大。

公开(公告)号：EP2446430A2

公开(公告)日：2012-05-02

申请号：EP10725355.1

申请日：2010-06-17

申请人： Global OLED Technology LLC

发明人： COK, Ronald, S.

IPC分类号： G09G3/32 ,  H01L27/32

CPC分类号： G09G3/3216 ,  G09G3/2085 ,  G09G3/3266 ,  G09G3/3275 ,  G09G2300/0465 ,  G09G2310/0221 ,  G09G2310/0278 ,  G09G2310/0286 ,  G09G2320/0247 ,  H01L27/3255

摘要： A passive-matrix display device having a plurality of chiplets, each chiplet associated with one or more independent column electrodes located in the display area, each chiplet electrically connected to and driving a separate subset of the independent column electrodes and electrically connected to and driving a subset of the row electrodes to cause the light-emitting material in each pixel to emit light, wherein each chiplet includes a serial luminance shift register for shifting pixel luminance values corresponding to each independent column electrode from one chiplet to another and a column driver for driving each of the independent column electrodes to which it is connected with the corresponding pixel luminance values; and wherein each chiplet further includes a row driver for driving each corresponding row electrode to which it is connected and a row control shift register for controlling the row drivers.

公开(公告)号：EP2444974A1

公开(公告)日：2012-04-25

申请号：EP10789123.6

申请日：2010-02-22

申请人： Sharp Kabushiki Kaisha

发明人： YONEMARU, Masashi ,  NAKAMIZO, Masahiko

IPC分类号： G11C19/28 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

摘要： Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. Each stage (Xi) of the shift register includes a first output transistor (M5), a second output transistor (M7), a first capacitor (of), a second capacitor (C2), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), a fourth switching element (M6), and a fifth switching element (M8).

摘要翻译： 公开了一种可以抑制每个级的输出噪声而不引起电路规模增加的移位寄存器和显示装置。 移位寄存器的每个级（Xi）包括第一输出晶体管（M5），第二输出晶体管（M7），第一电容器（第二电容器），第二电容器（C2），输入栅极（M1） 元件（M2），第二开关元件（M3），第三开关元件（M4），第四开关元件（M6）和第五开关元件（M8）。

公开(公告)号：EP2226938A4

公开(公告)日：2011-07-20

申请号：EP08792729

申请日：2008-08-26

申请人： SHARP KK

发明人： MURAKAMI YUHICHIROH ,  SASAKI YASUSHI ,  FURUTA SHIGE

IPC分类号： H03K17/06 ,  G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H03K17/00 ,  H03K17/16 ,  H03K17/693

CPC分类号： G09G3/3677 ,  G09G3/3655 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G11C19/184 ,  G11C19/28 ,  H03K17/063 ,  H03K17/165 ,  H03K17/693

公开(公告)号：EP2234100A3

公开(公告)日：2011-06-01

申请号：EP10156273.4

申请日：2010-03-12

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Kimura, Hajime ,  Umezaki, Atsushi

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/28

摘要： It is an object to suppress deterioration of characteristics of a transistor in a signal line or a scan driver circuit. A first switch for controlling whether to set a potential state of an output signal by being turned on and off in accordance with the first input signal, and a second switch for controlling whether to set a potential state of an output signal by being turned on and off in accordance with the second input signal are included. A first wiring and a second wiring are brought into electrical continuity by turning on and off of the first switch or the second switch.

公开(公告)号：EP2266118A1

公开(公告)日：2010-12-29

申请号：EP09735170.4

申请日：2009-03-31

申请人： Sharp Kabushiki Kaisha

发明人： The designation of the inventor has not yet been filed

IPC分类号： G11C19/00 ,  G09G3/20 ,  G11C19/28

CPC分类号： G11C19/28 ,  G09G3/20 ,  G09G3/3674 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2340/0492

摘要： A shift register comprises cascade-connected stages, each of which comprises a data latch (44) and an output stage. The latch (44) has a single data input (S) which, in use, receives a date signal from a preceding or succeeding stage. The output stage comprises a first switch (56), which passes a clock signal (CK2) to the stage output (GL) when the output stage is activated by the latch. The output stage also comprises a second switch (58), which passes the lower supply voltage (Vss) to the stage output (GL) when the output stage is inactive.

公开(公告)号：EP2256721A1

公开(公告)日：2010-12-01

申请号：EP08873495.9

申请日：2008-12-17

申请人： Sharp Kabushiki Kaisha

发明人： MIZUNAGA, Takayuki ,  MORII, Hideki ,  IWAMOTO, Akihisa ,  HIROKANE, Masahiro ,  OHTA, Yuuki

IPC分类号： G09G3/36 ,  G02F1/133 ,  G09G3/20

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2330/025 ,  G11C19/184 ,  G11C19/28

摘要： A display panel drive circuit includes a shift register (10a) constructed of unit circuits (SC1 to SCm) connected in stages. The unit circuits generate signal line selection signals (G1 to Gm), respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. Each of the unit circuits receive (i) clock signals (CK1 and CK2) generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal (GSP) generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal (CLR). The clear signal (CLR) is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register (10a) until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal (VSYNC, HSYNC, or DE).

摘要翻译： 一种显示面板驱动电路包括被构造在连接阶段单位电路（SC1至SCM）的移位寄存器（10a）中。 单位电路生成该信号线选择信号的时间respectivement某些周期，以形成respectivement脉冲制成有源信号线选择信号（G1到Gm），分别为和脉冲相继从respectivement单位电路中的顺序输出 序数从第一阶段开始，直到阶段结束。 各单位电路的接收（I）的时钟信号（CK1和CK2）的基础上的同步信号生成的来自所述显示面板驱动电路的外部接收的，（ⅱ）一个启动脉冲信号（GSP）基础上产生同步信号，或 在从自己的其它级生成的信号线选择信号，以及（iii）一个明确的信号（CLR）。 清零信号（CLR）在anomalousness被包括在同步信号的情况下被激活，并且没有脉冲从所述移位寄存器（10A）直到随后的垂直扫描期间开始的输出。 这种构造获得防止显示紊乱或按住给电源中负荷增大，其每一个的发生在anomalousness被包括在同步信号（VSYNC，HSYNC，或DE）的情况下的显示面板驱动电路。