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    METHOD AND MEANS OF DEAD TIME REDUCTION IN HALF BRIDGE TOPOLOGY
    4.
    发明公开
    METHOD AND MEANS OF DEAD TIME REDUCTION IN HALF BRIDGE TOPOLOGY 审中-实审

    公开(公告)号：EP4398486A1

    公开(公告)日：2024-07-10

    申请号：EP23211016.3

    申请日：2023-11-20

    申请人： Analog Devices International Unlimited Company

    发明人： STRZALKOWSKI, Bernhard

    IPC分类号： H03K17/16 ,  H02M1/38 ,  H03K17/284

    CPC分类号： H02M1/38 ,  H03K17/162 ,  H03K17/284 ,  H02M1/08

    摘要： There is provided a method of controlling a power converter or a power inverter, comprising: using a comparator to detect a negative voltage drop at a gate of a passive switch device, the negative voltage drop being indicative of an active switch device turning off; applying an adjustment time to a predetermined turn on time of the passive switch device so as to reduce the resultant dead time; and turning on the passive device once the resultant dead time has elapsed. There is also provided method of controlling a power converter or a power inverter, comprising: determining, by a microcontroller, an active switch device turning on; applying an adjustment time to a predetermined turn off time of a passive switch device so as to reduce the resultant dead time; and turning off the passive device once the resultant dead time has elapsed.

    USING DIFFERENT VOLTAGE LEVELS TO CLOSE A SWITCH IN A SWITCH CONVERTER
    7.
    发明公开
    USING DIFFERENT VOLTAGE LEVELS TO CLOSE A SWITCH IN A SWITCH CONVERTER 审中-公开

    公开(公告)号：EP4369605A1

    公开(公告)日：2024-05-15

    申请号：EP23207957.4

    申请日：2023-11-06

    申请人： Qorvo US, Inc.

    发明人： NOGAWA, Masashi

    IPC分类号： H03K17/16 ,  H02M1/08 ,  H03K17/06

    CPC分类号： H03K17/162 ,  H03K2017/06620130101 ,  H02M1/08 ,  H03K2217/008120130101 ,  H02M3/158 ,  H02M1/0029

    摘要： Embodiments of a switching circuitry are disclosed. In some embodiments, the switching circuitry includes a switch and a switch control circuit. The switch has a control terminal. The driver circuit is configured to initially apply a first voltage at a first voltage level to the control terminal so that the switch goes from being open to being closed. The driver circuit is configured to apply a second voltage at a second voltage level in response to the first voltage causing a voltage at the control terminal of the switch to reach a threshold voltage level, wherein the second voltage level is smaller in magnitude than the first voltage level. By using a higher voltage level when initially closing the switch, the switch is closed quickly. Once the switch is closed a lower voltage level is used to maintain the switch closed.

    CIRCUIT FOR CONTROLLING THE SLEW RATE OF A TRANSISTOR
    8.
    发明公开
    CIRCUIT FOR CONTROLLING THE SLEW RATE OF A TRANSISTOR 审中-实审

    公开(公告)号：EP4354733A2

    公开(公告)日：2024-04-17

    申请号：EP23196216.8

    申请日：2023-09-08

    申请人： GlobalFoundries U.S. Inc.

    发明人： Sharma, Santosh

    IPC分类号： H03K17/16 ,  H03K17/687

    CPC分类号： H03K17/162 ,  H03K17/165 ,  H03K17/163 ,  H03K17/168 ,  H03K17/6871 ,  H03K2017/687520130101

    摘要： Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.

    VERFAHREN UND VORRICHTUNG ZUM BETREIBEN EINER HALBBRÜCKENSCHALTUNG AUS DISKRETEN MOSFETS
    9.
    发明公开
    VERFAHREN UND VORRICHTUNG ZUM BETREIBEN EINER HALBBRÜCKENSCHALTUNG AUS DISKRETEN MOSFETS 审中-公开

    公开(公告)号：EP4350998A1

    公开(公告)日：2024-04-10

    申请号：EP23196729.0

    申请日：2023-09-12

    申请人： Volkswagen Aktiengesellschaft

    发明人： Arnaout, Samy

    IPC分类号： H03K17/30 ,  H03K17/0812 ,  H03K17/12 ,  H03K17/284 ,  H03K17/08 ,  H03K17/06 ,  H03K17/16 ,  H02M1/088 ,  H03K17/14

    摘要： Die Erfindung betrifft ein Verfahren zum Betreiben einer Halbbrückenschaltung (2) aus diskreten MOSFETs (T1 - T4), wobei die Halbbrückenschaltung (2) mindestens zwei parallelgeschaltete High-Side-Schalter und mindestens zwei parallelgeschaltete Low-Side-Schalter aufweist, wobei die MOSFETs (T1 - T4) mittels mindestens eines Gate-Treiberbausteins (3, 4) angesteuert werden, wobei die Gate-Anschlüsse (G1 - G4) der MOSFETs (T1 - T4) einzeln herausgeführt sind, wobei den Gate-Anschlüssen (G1 - G4) zuund einstellbare Widerstände (R) zugeordnet sind, wobei beim Einschalten der High-Side-Schalter die Gate-Source-Spannungen an den Low-Side-Schaltern und beim Einschalten der Low-Side-Schalter die Gate-Source-Spannungen an den High-Side-Schaltern erfasst werden, wobei die Gate-Source-Spannungen der High-Side-Schalter untereinander und die Gate-Source-Spannungen der Low-Side-Schalter untereinander verglichen werden, um ein jeweiliges PTO-Verhalten zu bestimmen, wobei bei einem abweichenden Verhalten mindestens ein Widerstand (R) verändert und/oder zeitlich verändert zugeschaltet wird, um das PTO-Verhalten anzugleichen, sowie eine Vorrichtung (1).