公开(公告)号：EP0453355B1

公开(公告)日：1999-01-27

申请号：EP91400976.6

申请日：1991-04-11

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： Goldstein, Fred Richard ,  Callon, Ross

IPC: H04L12/56

CPC classification number: H04L47/724 ,  H04J3/1629 ,  H04J3/247 ,  H04L12/5602 ,  H04L47/70 ,  H04L47/748 ,  H04L47/826 ,  H04L2012/5632 ,  H04L2012/5651 ,  H04L2012/5672 ,  H04Q11/0478

公开(公告)号：EP0788696B1

公开(公告)日：1998-11-25

申请号：EP93921738.6

申请日：1993-03-30

Applicant: NOKIA TELECOMMUNICATIONS OY

Inventor： SAIJONMAA, Jaakko ,  PYHÄLAMMI, Seppo

IPC: H04L12/56

CPC classification number: H04J3/247 ,  H04J2203/0048 ,  H04J2203/0089 ,  H04L25/14 ,  H04L2012/5615 ,  H04L2012/5646 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04Q11/0478

Abstract: The invention relates to a method for establishing a user-network interface in a digital transmission network for a cell-based digital 140 or 155 Mbit/s ATM signal, and a network interface embodying the method. The interface according to the invention comprises an input buffer (22) controlled by a predetermined policing function for receiving the cell-based signal and adapting the transmission speed of the signal to the actual transmission speed of the transmission network; a mapping means (31) for forming cell blocks of N consecutive cells from the cell-based signal and for adding N overhead bytes to each cell block; and a multiplexer (32) for multiplexing the output signal of the mapping means byte by byte into N separate output signals of about 1.5 Mbit/s, 2 Mbit/s, 6 Mbit/s or 8 Mbit/s.

公开(公告)号：EP0858240A2

公开(公告)日：1998-08-12

申请号：EP97118167.2

申请日：1997-10-20

Applicant: FUJITSU LIMITED

Inventor： Ishihara, Tomohiro ,  Ono, Hideaki ,  Kato, Tsuguo ,  Takechi, Ryuichi

IPC: H04Q11/04

CPC classification number: H04L49/3081 ,  H04J3/247 ,  H04L2012/5607 ,  H04L2012/5616 ,  H04L2012/5656 ,  H04L2012/5671 ,  H04Q11/0478

Abstract: A cell assembly and multiplexing device includes short cell assembly parts which store input information received via respective input lines and add short cell headers to the input information so that short cells having the short cell headers are assembled, and a multiplexing part which arranges the short cells in given fields of standard cells having a given standard format and a fixed cell length and outputs the standard cells having the short cells to a transmission line.

Abstract translation: 单元组合和多路复用装置包括短信元组合部分，其存储经由各个输入线接收的输入信息，并向输入信息添加短信元报头，以便组装具有短信元报头的短信元;以及复用部分， 在具有给定标准格式和固定单元长度的标准单元的给定字段中，将具有短单元的标准单元输出到传输线。

公开(公告)号：EP0788716A1

公开(公告)日：1997-08-13

申请号：EP95936001.0

申请日：1995-10-23

Applicant: MATRA COMMUNICATION

Inventor： MASSON, Jean-Michel ,  GRENIER, Frédéric

IPC: H04J3 ,  H04N7

CPC classification number: H04N21/4347 ,  H04J3/247 ,  H04N21/236 ,  H04N21/2365 ,  H04N21/434

Abstract: A device including a plurality of packetising modules supplying packet memories (PMi) from digital input streams, and multiplexing means (14) for selecting the packet memories from which the multiplex packets are to be retrieved and transferring them sequentially to a device output. Each packet in a packet memory is combined with selection parameters calculated by its packetising module and indicating at least an earliest time, a latest time and preferably an ideal time for transmission of the packet by the multiplexing means. The multiplexing means select the memory from which each multiplex packet is to be retrieved on the basis of the packet transmission time and the respective selection parameters combined with the first packets on stand-by in each of the packet memories.

公开(公告)号：EP0762799A3

公开(公告)日：1997-07-02

申请号：EP96113534.0

申请日：1996-08-23

Applicant: FUJITSU LIMITED

Inventor： Nomura, Yuji ,  Abe, Shunji

IPC: H04Q11/04 ,  H04L12/56 ,  H04J3/24

CPC classification number: H04L49/253 ,  H04J3/247 ,  H04J2203/0005 ,  H04J2203/0012 ,  H04J2203/0069 ,  H04L49/30 ,  H04L2012/5632 ,  H04L2012/5672 ,  H04Q11/0478

Abstract: A burst transfer system realizes burst transfer between communication terminals in a communication network of the label multiplex system or the time-division multiplex type. In the burst transfer system, the communication terminal is so designed as to output a communication reservation request which is made up of destination information including the address of the transmitting side communication terminal and the address of the receiving side communication terminal, and band information representing the start time, the use band of the burst transfer, etc. The burst transfer system includes request receiving means for receiving the communication reservation request; communication request analyzing means for extracting destination information and the band information from the communication reservation request received by the request receiving means; path setting means for discriminating paths through which the transmitting side communication terminal and the receiving side destination are connectable to each other on the basis of the destination information; and band reserving means, if a path that satisfies a condition indicated by the band information exists in the paths which are discriminated by the path setting means, for reserving the path.

公开(公告)号：EP0756796A1

公开(公告)日：1997-02-05

申请号：EP95917143.0

申请日：1995-04-18

Applicant: Multi-Tech Systems Inc

Inventor： ARIMILLI, Harinarayana ,  THANAWALA, Ashish, A. ,  KANCHAN, Vasant, Kumar

IPC: H04J3 ,  H04L29 ,  H04M1 ,  H04M11 ,  H04N1 ,  H04L12

CPC classification number: H04N1/00281 ,  H04J3/1688 ,  H04J3/247 ,  H04L29/06 ,  H04L2012/6427 ,  H04L2012/6459 ,  H04L2012/6462 ,  H04L2012/6464 ,  H04L2012/6486 ,  H04L2012/6494 ,  H04M1/253 ,  H04M11/064 ,  H04N1/00302 ,  H04N1/00312 ,  Y10S370/916

Abstract: A data multiplexing network is described which multiplexes a plurality of asynchronous data channels with an asynchronous data stream representing compressed voice signals and/or facsimile signals onto a single synchronous data packet stream. The single synchronous data packet stream is then transmitted by a high speed statistical multiplexer over a composite link to a second site using a modified high-level synchronous data link control protocol with an overlay of an advanced priority statistical multiplexing algorithm. The asynchronous data channels and the compressed voice channel and/or facsimile signals are demultiplexed and reconstructed for sending to other asynchronous computer terminals and to a standard telephone or facsimile analog port at the second site, respectively. PBX trunk interfaces are also provided to allow PBX's to share the composite link between sites. Communication between the first site by voice or facsimile and the second site is transparent to the users. The multiplexer efficiently allocates the bandwidth of the composite link by detecting silence periods in the voice signals and suppressing the sending of the voice information to preserve bandwidth. An advanced priority statistical multiplexer is also described which dynamically allocates composite link bandwidth to both time-sensitive and non-time-sensitive data to maximize data throughout efficiency and quality while simultaneously reducing multiplexer processing overhead.

公开(公告)号：EP0717909A1

公开(公告)日：1996-06-26

申请号：EP95921952.0

申请日：1995-06-29

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： BLOKS, Rudolf, Henricus, Johannes ,  VLOT, Marnix, Claudius

IPC: H04J3 ,  H04L7 ,  H04L12 ,  H04N7

CPC classification number: H04L12/40058 ,  H04J3/247 ,  H04L12/40117 ,  H04L12/407 ,  H04L12/417 ,  H04L12/64 ,  H04L12/6418 ,  H04L2012/6435 ,  H04L2012/6456 ,  H04L2012/6483 ,  H04L2012/6489 ,  H04N19/42 ,  H04N19/61 ,  H04N21/4135 ,  H04N21/4305 ,  H04N21/4307 ,  H04N21/4342 ,  H04N21/43632

Abstract: A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output, the system being characterized, in that it comprises a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus comprising a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit, the destination apparatus comprising a buffer, for buffering the signal prior to synchronizing the time-value of the clock for a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant the signal is supplied to the first interface unit.

公开(公告)号：EP0596624A3

公开(公告)日：1995-11-29

申请号：EP93308342.0

申请日：1993-10-20

Applicant: AT&T Corp.

Inventor： Sriram, Kotikalapudi

IPC: H04L12/56 ,  H04Q11/04

CPC classification number: H04N21/23655 ,  H04J3/247 ,  H04L2012/5616 ,  H04L2012/5632 ,  H04L2012/5638 ,  H04L2012/564 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04N21/2365 ,  H04N21/4347 ,  H04Q11/0478

Abstract: A wide variety of call traffic is effectively integrated in a single broadband communications network. Calls having widely differing bandwidth requirements and sensitivities to delay are handled by the network with efficient, effective, and fair bandwidth allocation and transmission scheduling. This is accomplished by classifying each call in accordance with certain signal characteristics, such as required bandwidth and sensitivity to delay. Each call class is directed to a separate queuing circuit. Some calls in certain classes, such as those associated with high-bandwidth constant bit rate services, are each directed to their own individual queuing circuits. Other calls within a class are statistically multiplexed into a single queuing circuit for that class. A multiplexing circuit operates in accordance with a dynamic time slice scheme which involves defining a service cycle time period during which the multiplexer withdraws a predetermined number of information packets from each of a plurality of queuing circuits containing information packets and places those predetermined numbers of packets onto an output link. The multiplexer breaks up the cycle time period into a plurality of time slices, each of which determines how many information packets are transmitted from each queuing circuit during the cycle time period. Efficient resource usage and congestion avoidance are further achieved by using one of a number of alternative scheduling techniques for delay insensitive traffic.

公开(公告)号：EP0649581A1

公开(公告)日：1995-04-26

申请号：EP94914477.0

申请日：1994-05-06

Applicant: GPT LIMITED

Inventor： CHOPPING, Geoffrey

IPC: H04J3 ,  H04L12 ,  H04Q11

CPC classification number: H04J3/08 ,  H04J3/12 ,  H04J3/1617 ,  H04J3/247 ,  H04J2203/005 ,  H04J2203/0089 ,  H04L2012/5672

Abstract: A pure ATM based multiplex is incapable, especially at low carrier rates, of satisfactorily carrying constant bit rate traffic or human communication traffic. A multiplex format having a plurality of constant bit rate timeslots in which a timeslot is not in use for constant bit rate traffic can have that timeslot used for message based traffic to provide a composite constant bit rate/message based data stream.

公开(公告)号：EP0641099A1

公开(公告)日：1995-03-01

申请号：EP94113129.4

申请日：1994-08-23

Applicant: Alcatel SEL Aktiengesellschaft

Inventor： Willmann, Gert ,  Wippenbeck, Matthias ,  Schrodi, Karl

IPC: H04J3/16

CPC classification number: H04J3/247 ,  H04L2012/5647 ,  H04L2012/5651 ,  H04L2012/5672 ,  H04L2012/5681 ,  H04Q11/0478

Abstract: Bei Überlastsituationen ist die Verlustwahrscheinlichkeit für Datenpakete (D4-D8) in allen Warteschlangen (QU1,QU2) in etwa gleich groß. Die Verlustwahrscheinlichkeit ist nicht abstufbar.
Datenpakete (D4-D8) werden in mehreren logischen Warteschlangen (QU1,QU2) zwischengespeichert, denen die Speicherplätze eines gemeinsamen Pufferspeichers (MEM) dynamisch zugeteilt werden.
Der unvermeidliche Verlust von Datenpaketen wird durch gezieltes Verwerfen von Datenpaketen systematisiert.
Ein in einer Warteschlange (QU2) niedriger Priorität gespeichertes Datenpaket (D6-D8) wird gelöscht, wenn ein ankommendes Datenpaket (D1) einer Warteschlange (QU1) höherer Priorität zugeordnet ist und die Gesamtlänge der Warteschlangen eine gewisse Länge überschritten hat.

Puffer mit verschiedenen, einstellbaren Zugangskontroll- oder Bedienverfahren kann einfach realisiert werden.
Schnelle Lösung, für ATM geeignet.

Abstract translation: 在过载条件下，数据包（D4-D8）的丢失的概率在所有队列相等的幅度（QU1，QU2）的约。 损失概率无法进行分级。 数据包（D4-D8）被暂时存储在一个数哪些是动态分配一个公共缓冲器存储器（MEM）的存储位置的逻辑队列（QU1，QU2）的。 数据分组的不可避免的损失是由数据分组的选择性排除系统化。 存储在低优先级队列（QU2）的数据分组（D6-D8）被删除当进入的数据分组（D 1）被分配到一个更高的优先级队列（QU1）和队列的总长度已超过一定的长度 ， - 与各种可调节的访问控制或操作过程的缓冲可以以简单的方式来实现。 - 快速解决方案，适用于ATM。