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公开(公告)号：EP0951671A1
公开(公告)日：1999-10-27
申请号：EP98929596.0
申请日：1998-07-16
Applicant: Koninklijke Philips Electronics N.V.
Inventor： VLOT, Marnix, Claudius , LIPPENS, Paul, Eugene, Richard
CPC classification number: G06F7/785 , G06F9/30058 , G06F9/30163 , G06F9/322 , G06F9/5016
Abstract: In an instruction a relative jump distance is expressed as a number of instructions rather than as a number of addresses. Instructions have various lengths. After encountering the instruction the processing device loads the following instructions but suppresses execution of a set of instructions that consists of the number of instructions expressed in the relative jump instruction.
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2.发明公开DATA PROCESSING SYSTEM WITH REDUCED LOOK-UP TABLE FOR A FUNCTION WITH NON-UNIFORM RESOLUTION 失效数据处理系统临时查找表软硬不均解决方案合作。
公开(公告)号：EP0660953A1
公开(公告)日：1995-07-05
申请号：EP94918493.0
申请日：1994-07-04
Applicant: PHILIPS ELECTRONICS N.V.
CPC classification number: G06F1/0353 , G06F1/035
Abstract: A data processing system with a look-up table means for implementing a transfer function with non-uniform resolution comprises a memory to store a plurality of function data; an input to receive external address words for operating on the memory; and an output to provide the function data. The look-up table means comprises a converging means between the input and the memory for mapping specific ones of the external address words onto a specific one of internal address words to access the memory. This greatly reduces memory size. If the transfer function has a symmetry property, a symmetry-handling means further reduces the memory size.
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公开(公告)号：EP0931286B1
公开(公告)日：2003-07-30
申请号：EP98928490.6
申请日：1998-07-06
Applicant: Koninklijke Philips Electronics N.V.
Inventor： VLOT, Marnix, Claudius , LIPPENS, Paul, Eugene, Richard
CPC classification number: G06F7/785 , G06F9/3013 , G06F9/30134 , G06F9/30163 , G06F9/30167 , G06F9/38 , G06F9/5016
Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.
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公开(公告)号：EP0877981A1
公开(公告)日：1998-11-18
申请号：EP97941140.0
申请日：1997-10-02
Applicant: Koninklijke Philips Electronics N.V.
Inventor： ZANDVELD, Frederik , VLOT, Marnix, Claudius
CPC classification number: G06F9/3804 , G06F12/0607
Abstract: Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are being read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.
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Patent Agency Ranking
公开(公告)号：EP0877981B1
公开(公告)日：2004-01-07
申请号：EP97941140.2
申请日：1997-10-02
Applicant: Koninklijke Philips Electronics N.V.
Inventor： ZANDVELD, Frederik , VLOT, Marnix, Claudius
CPC classification number: G06F9/3804 , G06F12/0607
Abstract: Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are being read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.
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公开(公告)号：EP0931286A1
公开(公告)日：1999-07-28
申请号：EP98928490.0
申请日：1998-07-06
Applicant: Koninklijke Philips Electronics N.V.
Inventor： VLOT, Marnix, Claudius , LIPPENS, Paul, Eugene, Richard
CPC classification number: G06F7/785 , G06F9/3013 , G06F9/30134 , G06F9/30163 , G06F9/30167 , G06F9/38 , G06F9/5016
Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.
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7.发明授权DATA PROCESSING SYSTEM WITH REDUCED LOOK-UP TABLE FOR A FUNCTION WITH NON-UNIFORM RESOLUTION 失效数据处理系统临时查找表软硬不均解决方案WORKING
公开(公告)号：EP0660953B1
公开(公告)日：2001-10-17
申请号：EP94918493.1
申请日：1994-07-04
Applicant: Koninklijke Philips Electronics N.V.
CPC classification number: G06F1/0353 , G06F1/035
Abstract: A data processing system with a look-up table means for implementing a transfer function with non-uniform resolution comprises a memory to store a plurality of function data; an input to receive external address words for operating on the memory; and an output to provide the function data. The look-up table means comprises a converging means between the input and the memory for mapping specific ones of the external address words onto a specific one of internal address words to access the memory. This greatly reduces memory size. If the transfer function has a symmetry property, a symmetry-handling means further reduces the memory size.
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公开(公告)号：EP0717909B1
公开(公告)日：2000-03-15
申请号：EP95921952.8
申请日：1995-06-29
Applicant: Koninklijke Philips Electronics N.V.
IPC: H04N7/58 , H04L12/417
CPC classification number: H04L12/40058 , H04J3/247 , H04L12/40117 , H04L12/407 , H04L12/417 , H04L12/64 , H04L12/6418 , H04L2012/6435 , H04L2012/6456 , H04L2012/6483 , H04L2012/6489 , H04N19/42 , H04N19/61 , H04N21/4135 , H04N21/4305 , H04N21/4307 , H04N21/4342 , H04N21/43632
Abstract: A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output, the system being characterized, in that it comprises a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus comprising a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit, the destination apparatus comprising a buffer, for buffering the signal prior to synchronizing the time-value of the clock for a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant the signal is supplied to the first interface unit.
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公开(公告)号：EP0717909A1
公开(公告)日：1996-06-26
申请号：EP95921952.0
申请日：1995-06-29
Applicant: PHILIPS ELECTRONICS N.V.
CPC classification number: H04L12/40058 , H04J3/247 , H04L12/40117 , H04L12/407 , H04L12/417 , H04L12/64 , H04L12/6418 , H04L2012/6435 , H04L2012/6456 , H04L2012/6483 , H04L2012/6489 , H04N19/42 , H04N19/61 , H04N21/4135 , H04N21/4305 , H04N21/4307 , H04N21/4342 , H04N21/43632
Abstract: A signal processing system comprising a source apparatus coupled to a destination apparatus, the source apparatus being arranged for supplying the destination apparatus with a signal comprising video data, a time-stamp and synchronization data representing a time-value of an instant of said supplying, the destination apparatus being arranged for receiving the signal, synchronizing a time-value of a clock in accordance with the synchronization data, detecting when the time-value of the clock corresponds to the time-stamp and for thereupon presenting the video data at an output, the system being characterized, in that it comprises a bus operable according to a time-slot allocation protocol, the source apparatus supplying the signal to the destination apparatus via the bus, the source apparatus comprising a first interface unit for buffering the signal until an allocated time-slot is available on the bus, the source apparatus setting the synchronization data according to an instant the signal is supplied to the first interface unit, the destination apparatus comprising a buffer, for buffering the signal prior to synchronizing the time-value of the clock for a predetermined interval, at least equal to a maximum wait-interval for the allocation of a time-slot on the bus, has elapsed after the instant the signal is supplied to the first interface unit.
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