公开(公告)号：EP0663117A4

公开(公告)日：1995-11-02

申请号：EP93922382

申请日：1993-09-24

申请人： CIRRUS LOGIC INC

发明人： BEHRENS RICHARD T ,  DUDLEY TRENT ,  GLOVER NEAL ,  WELLAND DAVID R

IPC分类号： G11B20/10 ,  G11B20/14 ,  H03D13/00 ,  H03L7/00 ,  H03L7/085 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04 ,  H04L7/10 ,  H03D3/24 ,  H03L7/06

CPC分类号： G11B20/10037 ,  G11B20/1403 ,  H03D13/005 ,  H03L7/091 ,  H04L7/0334 ,  H04L7/04 ,  H04L7/046 ,  H04L7/10

摘要： A timing circuit having an analog to digital converter (206) to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit (312) to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

公开(公告)号：EP0536301B1

公开(公告)日：1994-12-28

申请号：EP91913180.5

申请日：1991-06-28

申请人： ANALOG DEVICES, INCORPORATED

发明人： KOKER, Gregory, T. ,  TSANG, Steven, T.

IPC分类号： G06F1/04 ,  H03L7/085

CPC分类号： G06F1/10 ,  G06F1/06 ,  H03D13/004 ,  H03K5/13 ,  H03K5/26 ,  H03L7/0812 ,  H03L7/0895 ,  H03L7/0896

摘要： A phase detector (72), including multiple edge detectors (144, 146, 148), is provided for correction of any phase or frequency errors of a synchronous delay line clock generator (10). The edged detectors (144, 146, 148) provide an override of any corrective action by the rest of the phase detector to the synchronous delay line output, notwithstanding any phase error of less than 360°, if the phase position of the delay line output signal is off by an integral multiple of 360°. Taps (TAP 2, TAP 9, TAP 14) from daisy-chained or series-connected delay line elements (20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50) are provided to the phase detector (72). Each edge detector (144, 146, 148) compares the edge produced by a respective such tap against either one division of a divided clock signal or else the result of a previous such comparison. Apparatus and method are provided for saving a control signal for a signal-controlled system. The control signal is provided to a multiplexer (190), which normally outputs that control signal. That output is digitized and stored by a storage device (192) which produces a corresponding analog signal (VRLAD) as the other input to that multiplexer (190). A comparator (200) receives and compares the multiplexer (190) output and the analog signal (VRLAD). The comparator (200) thereby produces a signal (UP) to increment or decrement the stored signal.

公开(公告)号：EP0613253A1

公开(公告)日：1994-08-31

申请号：EP93309181.1

申请日：1993-11-17

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Guo, Bin

IPC分类号： H03L7/085 ,  H03L7/089

CPC分类号： H03D13/004

摘要： A novel method and apparatus providing an all digital phase comparator of two binary signals which employs a type of cross correlation of two binary signals and provides a 2bit binary word uniquely representative of phase alignment. The method can be carried out using a pair of flip-flop (FF) circuits, each FF having a clocking input and a data input, and where each FF has a delay in series with its data input.

摘要翻译： 一种提供两个二进制信号的全数字相位比较器的新型方法和装置，其采用两种二进制信号的互相关的一种类型，并提供唯一代表相位对准的2位二进制字。 该方法可以使用一对触发器（FF）电路进行，每个FF具有时钟输入和数据输入，并且其中每个FF具有与其数据输入串联的延迟。

公开(公告)号：EP0556984A1

公开(公告)日：1993-08-25

申请号：EP93300822.9

申请日：1993-02-04

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Gleichert, Marc C. ,  Korn, Thomas

IPC分类号： H04L7/033 ,  H03L7/081 ,  H03L7/085

CPC分类号： H04L7/0331 ,  H03L7/081 ,  H03L7/085

摘要： A phase detector (1) for a phase locked loop (PLL) for bit clock retrieval where the phase detector employs a plurality of variable unit delays (20,21) and has a constant gain region that is a percentage of the clock period over an extended frequency range of the VCO enabling a single (PLL) chip to operate for several applications at widely different frequencies.

摘要翻译： 一种用于位时钟检索的锁相环（PLL）的相位检测器（1），其中所述相位检测器采用多个可变单位延迟（20,21），并且具有恒定的增益区域，所述恒定增益区域是时钟周期的百分比 VCO的扩展频率范围，使得单个（PLL）芯片可以在广泛不同的频率下进行多种应用。

公开(公告)号：EP0522879A2

公开(公告)日：1993-01-13

申请号：EP92306377.0

申请日：1992-07-10

申请人： RAYTHEON COMPANY

发明人： Montress, Gary K. ,  Russell, Mark E.

IPC分类号： H03L7/085 ,  H03L7/20 ,  H03B5/32 ,  H03L7/099

CPC分类号： H03L7/20

摘要： A SAW stabilized oscillator (10) includes a phase locking circuit (38,16,20,22,36) which is phase locked to a lower frequency reference signal having an odd order difference with respect to the fundamental frequency of the SAW oscillator (14). A mixer (54) is disposed in the phase locking circuitry and is used as a sub-harmonic phase detector by mixing the fundamental (54a) with an odd harmonic (54b) of the reference signal (10a). The mixer output (54c) is filtered (70) and amplified (72,74) before being supplied to the control voltage input terminal (36′) of a voltage controlled variable phase shifter (36) in the SAW oscillator (14) loop (13).

摘要翻译： SAW稳压振荡器（10）包括相位锁定电路（38,16,20,22,36），锁相电路相对于SAW振荡器（14）的基频具有奇数阶差的较低频率参考信号 ）。 混频器（54）设置在锁相电路中，并通过将基波（54a）与参考信号（10a）的奇次谐波（54b）混合而用作次谐波相位检测器。 混频器输出（54c）在被提供给SAW振荡器（14）回路中的电压控制可变移相器（36）的控制电压输入端（36分钟）之前被滤波（70）并放大（72,74） 13）。

公开(公告)号：EP0474671A4

公开(公告)日：1992-01-13

申请号：EP90907725

申请日：1990-05-17

申请人： MOTOROLA INC

发明人： MARTIN FREDERICK L

IPC分类号： H03K5/26 ,  G01R25/00 ,  H03D13/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/097

CPC分类号： H03D13/004 ,  G01R25/00 ,  H03L7/087

公开(公告)号：EP4145705A1

公开(公告)日：2023-03-08

申请号：EP22179353.2

申请日：2019-06-12

申请人： Kandou Labs SA

发明人： GHARIBDOUST, Kiarash

IPC分类号： H03L7/08 ,  H03L7/085 ,  H03L7/089 ,  H04L25/03

摘要： Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.

公开(公告)号：EP3701631B8

公开(公告)日：2022-04-27

申请号：EP17822055.4

申请日：2017-12-19

发明人： YEO, Theng Tee ,  CHEN, Xuesong ,  YU, Rui ,  LIU, Supeng ,  YUAN, Chao

IPC分类号： H03L7/085 ,  H03L7/093 ,  H03L7/08

公开(公告)号：EP3975430A1

公开(公告)日：2022-03-30

申请号：EP21193062.3

申请日：2021-08-25

申请人： INTEL Corporation

发明人： SHUMAKER, Evgeny ,  DEGANI, Ofir ,  LEVINGER, Run ,  BERSHANSKY, Sergey

IPC分类号： H03L7/085 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099

摘要： An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.

公开(公告)号：EP3907891A1

公开(公告)日：2021-11-10

申请号：EP19848925.4

申请日：2019-01-02

申请人： BOE Technology Group Co., Ltd. ,  Beijing BOE Technology Development Co., Ltd.

发明人： WEI, Xiangye ,  XIU, Liming

IPC分类号： H03L7/18 ,  H03L7/085

摘要： A measuring device and a measuring method are provided. The measuring device (1) includes an oscillating circuit (11), a time average frequency-frequency lock loop (12), and a digital signal processing circuit. The oscillation circuit (11) includes an element to be measured and is configured to output a signal having an oscillation frequency correlated with an element value of the element to be measured. The time average frequency-frequency lock loop (12) is configured to receive the signal output by the oscillation circuit (11) and output a frequency control word correlated with the oscillation frequency. The digital signal processing circuit is configured to read the frequency control word output by the time average frequency-frequency lock loop (12) and obtain the element value of the element to be measured according to the read frequency control word. The measuring device (1) is easy to integrate, has small volume, low power consumption, and high reliability, and can achieve high-precision measurement.