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公开(公告)号：EP2414945A2
公开(公告)日：2012-02-08
申请号：EP10727989.5
申请日：2010-03-31
IPC分类号： G06F13/38
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to, and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs (1, 2, . . . , 8) of the control module (CM) are connected respectively to the asynchronous analog-to-digital converter (AADC), to the buffer memory module (BUF), to the source address module (SADR), to the configuration registers module (REG), to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and to the clock control module (SCM), and on the other hand, the transmitter/receiver module (SDM) output is connected through the controller (SDD) to the data line (SDA) of the I2C bus whose clock line (SCL) is connected through the other controller (SCD) to the clock control module (SCD) output, and what is more the write control output (9) of the asynchronous analog-to-digital converter (AADC) is connected to the write control input (10) of the buffer memory module (BUF).
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82.发明公开METHOD OF CONTROLLING ACCESS OF DEVICES TO COMMUNICATION MEDIUM IN DISTRIBUTED NETWORKS 有权一种用于在分布式网络中控制到通信媒介的装置的访问方法
公开(公告)号：EP2406921A1
公开(公告)日：2012-01-18
申请号：EP10714975.9
申请日：2010-03-13
发明人： MISKOWICZ, Marek
IPC分类号： H04L12/413
CPC分类号： H04L12/413
摘要： Each time before the packet transmission attempt, if the communication medium is detected to be idle, the prespecified fixed time interval equal to the minimum interpacket space is timed out during which the random numbers of time slots defining the order of media access are selected from the fixed number of slots of equal width using the pseudorandom number generator in every node where the probability of a selection of a particular slot is geometric with a characteristic parameter defined as the ratio of the probability of a selection of a given slot to the probability of a selection of the next slot, which changes from zero to one as a discrete function of the state of the node's counter, and after that the time interval of random delay corresponding to the selected random slot is assigned.
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公开(公告)号：EP0110194A2
公开(公告)日：1984-06-13
申请号：EP83111045.7
申请日：1983-11-04
IPC分类号： B21B19/12
CPC分类号： B21B19/12
摘要： ] Das Verfahren zur Verminderung der Rohrwanddicke besteht darin, daß in der Zone der Reduzierung der Wanddicke auf die Innenfläche des Rohres durch den Kopf des Dornes ein Druck ausgeübt wird, der die Erhöhung des Innendurchmessers bewirkt, und auf die Außenfläche des Rohres durch die Walzen ein Druck ausgeübt wird, welcher die Unveränderlichkeit des Außendurchmessers des Rohres gewährleistet.
Das Walzwerk zur Verminderung der Wanddicke des Rohres hat einen Erweiterungskopf (4), der auf einem Dorn (1) sitzt und Arbeitswalzen (6), weiche in der Reduzierungszone der Wanddicke des Rohres (2) eine Ballenoberfläche aufweisen, die zu der Achse des Rohres (2) parallel liegt. Die Lager (7) der Arbeitswalzen (6) sind radial verschiebbar in dem rotierenden Kopf (7) eingesetzt.摘要翻译： 降低管壁厚度的方法是，压力在减少管的内表面上的壁的厚度的区域中通过芯棒的头部施加引起的内径的增大，并在该管通过辊的外表面，一个压力 被施加其确保管的外径的不变性。 用于减小管的壁厚轧机有一个扩展头（4）坐在一个心轴（1）和在该管的壁厚的还原区具有工作辊（6）（2）具有球表面到管的轴线 （2）位于平行。 工作辊（6）的轴承（7）的沿径向可滑动地装配在旋转头（7）。
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公开(公告)号：EP4418053A1
公开(公告)日：2024-08-21
申请号：EP23163316.5
申请日：2023-03-21
IPC分类号： G04F10/00
CPC分类号： G04F10/005
摘要： An apparatus for clockless and direct conversion of a time interval to a digital word comprises: a control module (CM), two comparators (KR, KS), two current sources (IR, IS), two buses (R, S), two counter capacitors Cn-r, a set of n-r capacitors (Cn-r-1, ..., C0) with a binary capacitance ratio, two counter switches (Sn-r) and n-r switches of a set (Sn-r-1, ..., S0). The control module (CM) is equipped with an r-bit counter (Ct), whose outputs are connected directly to outputs of r most significant bits (bn-1, ..., br) of the n-bit output digital word (B).
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公开(公告)号：EP4198179B1
公开(公告)日：2024-08-21
申请号：EP22209761.0
申请日：2022-11-26
CPC分类号： D01D5/0007 , D04H1/728 , D01D5/0038 , A61F13/00063 , A61F13/01012
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公开(公告)号：EP4415243A1
公开(公告)日：2024-08-14
申请号：EP23159287.4
申请日：2023-03-01
发明人： Stala, Robert
摘要： The subject of the invention is a voltage step-down converter with an extended range of obtained stepped-down output voltages, comprising a capacitive input divider which constitutes a branch of three capacitors (1), (2) and (3) connected in series, connected between a positive input terminal (10) and a negative input terminal (11), wherein a negative output of the capacitor (1) included in the input capacitor divider connected to the negative input terminal (11) of supply voltage UIN and to an output of a controlled switch (5), whose output is connected to a negative output terminal (13) of stepped-down output voltage and to a negative input of an output capacitor (39), as well as to an input of a controlled switch (7) and to an anode of a diode (4). A positive input of the capacitor (3) is connected to the positive input terminal (10) of the supply voltage UIN and to an input of a controlled switch (6), whose output is connected to an input of a choke (18) and to an output of a controlled bidirectional switch (8) and to a cathode of a diode (9), whereas an output of the choke (18) is connected to a positive input of the output capacitor (39) and to a positive output terminal (12) of the stepped-down output voltage. Whereas to a connection point of the capacitors (2) and (3), a cathode of the diode (4) and an input of the controlled bidirectional switch (8) are connected, and to a connection point of the capacitors (1) and (2), an anode of the diode (9) and an output of the controlled bidirectional switch (7) are connected.
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公开(公告)号：EP4393848A1
公开(公告)日：2024-07-03
申请号：EP23164273.7
申请日：2023-03-27
摘要： The subject of the invention is a trough (1) of vibrating conveyor, which trough has closed profile, and comprise sensors distributed evenly in the trough (1) along the entire conveying path between the inlet and outlet openings, wherein one of compounding elements of each sensor such as: a transmitter (2) or a receiver (3) is mounted at the bottom, in the horizontal, flat bottom of the trough (1), and the other corresponding sensor element such as: a receiver (3) or a transmitter (2) is mounted in the opposite wall, at the top of the trough (1).
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公开(公告)号：EP4362313A1
公开(公告)日：2024-05-01
申请号：EP22213682.2
申请日：2022-12-15
发明人： Stala, Robert
IPC分类号： H02M7/487
CPC分类号： H02M7/487 , H02M7/483 , H02M7/5388
摘要： The subject of the invention is a multilevel diode-clamped voltage inverter having a minimized number of transistors, enabling multilevel modulation of output voltage, created by modifying a classic NPC-type inverter.
The modification of the three-phase diode-clamped NPC inverter has been implemented by attaching to it an additional system composed of a capacitive divider constituting a serial connection of capacitors C3 and C4, and three legs, each including one controlled bidirectional switch (S13, S14 and S15), that connect a common connection point of the capacitors C3 and C4 to individual phase legs of the NPC inverter.
The inverter according to the invention is implemented in four versions. In a first and a second version, the capacitive divider of the additional system replaces one of the capacitors of the input divider of the NPC inverter, and in a third and a fourth version it is connected in parallel to one of the capacitors of the input divider of the NPC inverter.
The voltage between the phases of the system, which is the voltage difference of two legs of the system, can take values: Uin, 4Uin/3, Uin/2, Uin/4, 0, - Uin/4, - Uin/2, -4 Uin/3, - Uin, that is, at 9 levels.-
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公开(公告)号：EP3534294B1
公开(公告)日：2023-09-06
申请号：EP18159762.6
申请日：2018-03-02
IPC分类号： G06V20/52 , G06V10/82 , G06V10/44 , G06V10/764
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