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公开(公告)号：EP3145087B1
公开(公告)日：2019-04-10
申请号：EP15201443.7
申请日：2015-12-18
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公开(公告)号：EP2577407B1
公开(公告)日：2017-08-09
申请号：EP11779239.0
申请日：2011-06-05
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公开(公告)号：EP3970616A1
公开(公告)日：2022-03-23
申请号：EP21197580.0
申请日：2021-09-18
摘要： The subject of the invention is a device for detecting the QRS complex of an ECG electrocardiogram signal applicable in biomedical diagnostics.
The device has ABS_DIFF_SHORT_MODULE 2 and ABS_DIFF_LONG_MODULE 3, the inputs of which are connected to the ECG_MODULE 1 measuring module output, and the ABS_DIFF_SHORT_MODULE 2 module output is connected to one of the COMP 4 comparator inputs, and the output of the ABS_DIFF_LONG_MODULE 3 module is connected to the input of the PEAK_DETECTOR 5 detection module. The COMP 4 comparator output is connected to the PULSE GENERATOR 6 pulse generator input. The output of the PULSE GENERATOR 6 pulse generator is connected to the gating input of the PEAK_DETECTOR detection module and to the R_AMPLITUDE_MEMORY 8 memory recording module input and to the R_TIMESTAMP_MEMORY 9 memory recording module input. The output of the PEAK_DETECTOR 5 detection module is also connected to the R_AMPLITUDE_MEMORY 8 and R_TIMESTAMP_MEMORY 9 memory module inputs, and the R_AMPLITUDE_MEMORY 8 memory module output is connected to the TH_MODULE 7 module input. The TH_MODULE 7 module output is also connected to one of the COMP 4 comparator inputs.-
4.发明公开METHOD AND APPARATUS FOR INDIRECT CONVERSION OF VOLTAGE VALUE TO DIGITAL WORD 审中-公开方法和装置的电压值在数字WORD间接转换
公开(公告)号：EP3145087A1
公开(公告)日：2017-03-22
申请号：EP15201443.7
申请日：2015-12-18
摘要： A method for indirect conversion of a voltage value to a digital word consisting in sampling an input voltage through a parallel connection of a sampling capacitor to a source of the input voltage, and next in mapping a sample value of the input voltage to a time interval, and in assignment of a corresponding value of n-bit output digital word by the use a control module characterized in that the time interval (T) is mapped to a difference of a length of a reference time (RT) and a length of a signal time (ST), while the reference time (RT) is generated from an instant (t 1 ) when the beginning of the time interval (T) is detected by the use the control module (CM), and the signal time (ST) is generated from an instant (t 2 ) when the end of the time interval (T) is detected by the use the control module (CM), whereas generation of the reference time (RT) and the signal time (ST) is terminated at the same instant (t 3 ).
摘要翻译： 一种用于电压值的数字字通过一个采样电容器的输入电压的源极并联连接在输入电压的采样由...组成间接变换方法，并且在输入电压的采样值映射到的时间间隔下 ，并在通过使用特征的控制模块所做的时间间隔（T）被映射到的一个基准时间的长度（RT）的差和一个长度为n位输出数字字的一个相应的值的分配 信号时间（ST），而该基准时间（RT）从在当通过使用控制模块（CM），和信号时检测到的时间间隔（T）的开始时刻（T 1）中生成（ST ）从（在时刻t 2）当通过使用控制模块（CM）检测到的时间间隔（T）的端部，而生成的基准时间（RT）和所述信号 - 时间（ST）被终止产生 在同一时刻（T 3）。
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公开(公告)号：EP2414945A2
公开(公告)日：2012-02-08
申请号：EP10727989.5
申请日：2010-03-31
IPC分类号： G06F13/38
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to, and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs (1, 2, . . . , 8) of the control module (CM) are connected respectively to the asynchronous analog-to-digital converter (AADC), to the buffer memory module (BUF), to the source address module (SADR), to the configuration registers module (REG), to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and to the clock control module (SCM), and on the other hand, the transmitter/receiver module (SDM) output is connected through the controller (SDD) to the data line (SDA) of the I2C bus whose clock line (SCL) is connected through the other controller (SCD) to the clock control module (SCD) output, and what is more the write control output (9) of the asynchronous analog-to-digital converter (AADC) is connected to the write control input (10) of the buffer memory module (BUF).
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6.发明公开METHOD OF CONTROLLING ACCESS OF DEVICES TO COMMUNICATION MEDIUM IN DISTRIBUTED NETWORKS 有权一种用于在分布式网络中控制到通信媒介的装置的访问方法
公开(公告)号：EP2406921A1
公开(公告)日：2012-01-18
申请号：EP10714975.9
申请日：2010-03-13
发明人： MISKOWICZ, Marek
IPC分类号： H04L12/413
CPC分类号： H04L12/413
摘要： Each time before the packet transmission attempt, if the communication medium is detected to be idle, the prespecified fixed time interval equal to the minimum interpacket space is timed out during which the random numbers of time slots defining the order of media access are selected from the fixed number of slots of equal width using the pseudorandom number generator in every node where the probability of a selection of a particular slot is geometric with a characteristic parameter defined as the ratio of the probability of a selection of a given slot to the probability of a selection of the next slot, which changes from zero to one as a discrete function of the state of the node's counter, and after that the time interval of random delay corresponding to the selected random slot is assigned.
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公开(公告)号：EP3096461B1
公开(公告)日：2020-08-05
申请号：EP15200621.9
申请日：2015-12-16
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8.发明公开METHOD AND APPARATUS FOR ENCODING ANALOG SIGNAL INTO TIME INTERVALS 审中-公开VERFAHREN UND VORRICHTUNG ZURI EDIES INNALOGSIGNALS IN ZEITINTERVALLEN
公开(公告)号：EP3096461A1
公开(公告)日：2016-11-23
申请号：EP15200621.9
申请日：2015-12-16
摘要： Method for encoding analog signal into time intervals consists in a generation of time intervals using a time encoding machine (TEM). A signal of a constant value is held during a generated time interval on a time encoding machine (TEM) input by the use of a sample-and-hold circuit SH, while the constant value of the signal held during the generated time interval represents an instantaneous value of the analog signal at the end of a generation of a previous time interval.
Apparatus for encoding analog signal into time intervals comprising a time encoding machine (TEM), and a sample-and-hold circuit (SH). The signal is provided to an input (SHin) of the sample-and-hold circuit (SH), whose output (SHout) is connected to an output (TEMin) of the time encoding machine (TEM). The output (TEMout) of the time encoding machine (TEM) is connected to an output (Out) of the apparatus, and to a control input (SHctr) of the sample-and-hold circuit (SH).摘要翻译： 将模拟信号编码成时间间隔的方法包括使用时间编码机（TEM）产生时间间隔。 在通过使用采样保持电路SH输入的时间编码机（TEM）的生成时间间隔内保持恒定值的信号，而在生成的时间间隔期间保持的信号的常数值表示 在前一时间间隔的生成结束时的模拟信号的瞬时值。 用于将模拟信号编码成包括时间编码机（TEM）和采样保持电路（SH）的时间间隔的装置。 信号被提供给采样保持电路（SH）的输出（SHin），其输出（SHout）连接到时间编码机（TEM）的输出（TEMin）。 时间编码机（TEM）的输出（TEMout）连接到装置的输出（Out），连接到采样保持电路（SH）的控制输入（SHctr）。
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9.发明授权METHOD AND APPARATUS FOR ANALOG-TO-DIGITAL CONVERSION USING ASYNCHRONOUS SIGMA-DELTA MODULATION 有权方法和设备模数转换使用一种异步sigma-delta调制
公开(公告)号：EP2140552B1
公开(公告)日：2012-10-10
申请号：EP08741773.9
申请日：2008-04-03
CPC分类号： H03M1/504 , H03M1/1215 , H03M3/43
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10.发明公开METHOD AND APPARATUS FOR ANALOG-TO-DIGITAL CONVERSION USING ASYNCHRONOUS SIGMA-DELTA MODULATION 有权方法和设备模数转换使用一种异步sigma-delta调制
公开(公告)号：EP2140552A2
公开(公告)日：2010-01-06
申请号：EP08741773.9
申请日：2008-04-03
IPC分类号： H03M3/02
CPC分类号： H03M1/504 , H03M1/1215 , H03M3/43
摘要： The solution according to the invention consisting in the modulation of the analog signal using the asynchronous Sigma-Delta modulator, counting periods of the reference clock during each pulse of the previously obtained square wave and making the digital word available is characterized in that the square wave (z(t)) obtained in result of the modulation in the asynchronous Sigma-Delta modulator (ASDM) is subjected to conversion by counting the periods (T0) of the reference clock (RG) during subsequent pulses of that square wave (z(t)) by means of the counting module (CTM), and then each word obtained representing the number of periods (T0) of the reference clock (RG) counted during each given pulse of the square wave (z(t)) is recorded and stored in the intermediate buffer (TBUF); and the duration of the serial transmission of the digital word obtained in result of counting the periods of the reference clock (RG) during previous pulse of the square wave (z(t)) is simultaneously controlled by the control module (CM); and as soon as this transmission is completed, the content of the intermediate buffer (TBUF) is transferred to the transmitting buffer (TDR) of the apparatus; and after that a given digital word representing a given pulse of the squarewave (z(t)) is transmitted serially to the computer or to the communication network; then the cycle is repeated for the next pulse of the square wave (z(t)).
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