公开(公告)号：EP1516243A4

公开(公告)日：2009-11-11

申请号：EP03761903

申请日：2003-06-26

申请人： US GOV SEC NAVY

发明人： BHARADWAJ RAMESH ,  SIMS STEVE

IPC分类号： G06F7/10 ,  G06F7/60 ,  G06F17/10 ,  G06F17/50

CPC分类号： G06F17/504

公开(公告)号：EP2012243A1

公开(公告)日：2009-01-07

申请号：EP07111858.2

申请日：2007-07-05

申请人： Honda Research Institute Europe GmbH

发明人： Gräning, Lars ,  Olhofer, Markus ,  Sendhoff, Bernhard

IPC分类号： G06F17/50 ,  F01D5/14

CPC分类号： G06F17/504 ,  F01D5/141

摘要： A computer-assisted method for analysing data representing the optimization of real-world designs according to at least one criterion, expressed in physical entities,
wherein
- by an iterative optimization algorithm modifications of the design are computed,
- the design data are represented by unstructured triangular surface meshes,
- a displacement measure representing the geometrical differences between at least design modifications is calculated,
- the performance differences, expressed by the at least one physical criterion, between said at least two design modifications is calculated, and
- a sensitivity information signal is output representing the interrelation between the displacement measure and the performance differences.

摘要翻译： 对于成绩分析数据代表真实世界的优化计算机辅助方法设计的雅鼎到至少一个标准，在物理实体来表达，worin - 通过在设计的迭代优化算法的修改计算， - 设计数据由非结构化代表 三角形的面啮合， - 代表至少设计修改之间的几何差异的位移测量被计算， - 的性能差异，由所述至少一个物理标准表达，所述至少两个之间的设计修改被计算，以及 - 一个感度信息信号 是表示位移度量和性能上的差异之间的相互关系输出。

公开(公告)号：EP1899877A2

公开(公告)日：2008-03-19

申请号：EP06785706.0

申请日：2006-06-27

申请人： Arithmosys, Inc.

发明人： MUKUND, Shridhar ,  MITRA, Anjan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

公开(公告)号：EP1661164A4

公开(公告)日：2007-10-31

申请号：EP04782461

申请日：2004-08-26

申请人： NUSYM TECHNOLOGIES INC

发明人： WILSON JAMES CHRISTOPHER ,  IMBODEN KENNETH W ,  GOLD DAVID

IPC分类号： G06F17/50 ,  H01L20060101

CPC分类号： G06F17/504

摘要： Methods and systems for performing symbolic simulation, including techniques for translating (230) a conventional simulation into a symbolic simulation, for handling wait and delay states, and for performing temporally out-of-order simulations. Additional techniques for extracting (245) a signal graph from an HDL representation (205) of a device, for representing signal values as functions of time using binary decision diagrams (250), and for computing minimal signal sets for accurate simulation. Techniques and methods for improving waveform dumping, reducing the waveform database, and for combining out of-order simulation or reduced time steps with conventional time-based simulation.

公开(公告)号：EP1843267A1

公开(公告)日：2007-10-10

申请号：EP07009047.7

申请日：2001-03-01

申请人： Cadence Design Systems, Inc.

发明人： Chao, Han-Hsun ,  Razdan, Rahul ,  Saldanha, Alexander

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/504

摘要： A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behaviour, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values. If the satisfiability engine fails to finish, then the simulation is run on the combinational logic, and an attempt is made to justify the values sequentially as well.

摘要翻译： 用于关键和错误路径验证的方法和设备采用所有可能的错误路径，并且仅为组合逻辑捕获使它们成为真实路径（或错误路径）作为布尔表达式（网络列表）的条件。 网表不一定要在门级，但可以是简化的门级表示，因为验证过程只涉及逻辑行为，而不是实际结构。 这允许模拟更快地执行。 由于条件只能在寄存器元素之间捕获，因此可以正式证明该路径是否可以被执行。 如果没有寄存器值可以激活路径，则分析完成。 否则，执行仿真以确定实际发生激活条件所需的寄存器值。 如果可以满足布尔条件，则在时序逻辑上执行仿真以证明这些值的正确性。 如果可满足性引擎未能完成，那么仿真将在组合逻辑上运行，并尝试对这些值依次进行验证。

公开(公告)号：EP0917032A3

公开(公告)日：2007-09-19

申请号：EP99100408.6

申请日：1994-10-28

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Kanno, Yuji

IPC分类号： G05B19/045 ,  G06F7/00 ,  G06F17/50 ,  G06K9/68 ,  G06F17/30

CPC分类号： G05B19/042 ,  G05B19/0426 ,  G05B19/045 ,  G05B2219/23289 ,  G05B2219/31451 ,  G05B2219/32165 ,  G05B2219/32166 ,  G05B2219/32353 ,  G06F7/00 ,  G06F17/504 ,  G06K9/68 ,  Y02P90/26 ,  Y10S707/99943

摘要： A constructing method of a finite state machine with failure transitions FFM is disclosed. The machine FFM is constructed from a nondeterministic finite-state machine and a string of external inputs. States in the machine FFM is formed of a state set q included in the nondeterministic finite-state machine and a set p defined as a subset of the state set q, and the number of states is finite. Also, an external input c takes the machine FFM from a current state s to a next state g(s,c) and an output µ(s) is output from the next state g(s,c) in cases where a value g(s,c) of a success function g is defined, and an external input c takes the machine FFM from the current state s to a state g(f(f···f(s)···)) determined by repeatedly calculating a value f(s) of a failure function f until a value g(f(f···f(s)···)) defined is found out in cases where the value g(s,c) of the success function g is not defined. Because all of transitions from the current state s for all external inputs c are not defined by the success function g, a storage capacity for storing the machine FFM is considerably reduced.

公开(公告)号：EP0917030A3

公开(公告)日：2007-09-19

申请号：EP99100406.0

申请日：1994-10-28

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Kanno, Yuji

IPC分类号： G05B19/045 ,  G06F7/00 ,  G06F17/50 ,  G06K9/68 ,  G06F17/30

CPC分类号： G05B19/042 ,  G05B19/0426 ,  G05B19/045 ,  G05B2219/23289 ,  G05B2219/31451 ,  G05B2219/32165 ,  G05B2219/32166 ,  G05B2219/32353 ,  G06F7/00 ,  G06F17/504 ,  G06K9/68 ,  Y02P90/26 ,  Y10S707/99943

摘要： A constructing method of a finite state machine with failure transitions FFM is disclosed. The machine FFM is constructed from a nondeterministic finite-state machine and a string of external inputs. States in the machine FFM is formed of a state set q included in the nondeterministic finite-state machine and a set p defined as a subset of the state set q, and the number of states is finite. Also, an external input c takes the machine FFM from a current state s to a next state g(s,c) and an output µ(s) is output from the next state g(s,c) in cases where a value g(s,c) of a success function g is defined, and an external input c takes the machine FFM from the current state s to a state g(f(f···f(s)···)) determined by repeatedly calculating a value f(s) of a failure function f until a value g(f(f···f(s)···)) defined is found out in cases where the value g(s,c) of the success function g is not defined. Because all of transitions from the current state s for all external inputs c are not defined by the success function g, a storage capacity for storing the machine FFM is considerably reduced.

公开(公告)号：EP0917029A3

公开(公告)日：2007-09-19

申请号：EP99100405.2

申请日：1994-10-28

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Kanno, Yuji

IPC分类号： G05B19/045 ,  G06F7/00 ,  G06F17/50 ,  G06K9/68 ,  G06F17/30

CPC分类号： G05B19/042 ,  G05B19/0426 ,  G05B19/045 ,  G05B2219/23289 ,  G05B2219/31451 ,  G05B2219/32165 ,  G05B2219/32166 ,  G05B2219/32353 ,  G06F7/00 ,  G06F17/504 ,  G06K9/68 ,  Y02P90/26 ,  Y10S707/99943

摘要： A constructing method of a finite state machine with failure transitions FFM is disclosed. The machine FFM is constructed from a nondeterministic finite-state machine and a string of external inputs. States in the machine FFM is formed of a state set q included in the nondeterministic finite-state machine and a set p defined as a subset of the state set q, and the number of states is finite. Also, an external input c takes the machine FFM from a current state s to a next state g(s,c) and an output µ(s) is output from the next state g(s,c) in cases where a value g(s,c) of a success function g is defined, and an external input c takes the machine FFM from the current state s to a state g(f(f···f(s)···)) determined by repeatedly calculating a value f(s) of a failure function f until a value g(f(f···f(s)···)) defined is found out in cases where the value g(s,c) of the success function g is not defined. Because all of transitions from the current state s for all external inputs c are not defined by the success function g, a storage capacity for storing the machine FFM is considerably reduced.

公开(公告)号：EP0908834B1

公开(公告)日：2006-08-16

申请号：EP98307486.5

申请日：1998-09-15

申请人： STMicroelectronics Ltd.

发明人： Barrett, Geoff

IPC分类号： G06F17/50

CPC分类号： G06F17/504

公开(公告)号：EP1681633A2

公开(公告)日：2006-07-19

申请号：EP05112489.9

申请日：2005-12-20

申请人： MICROSOFT CORPORATION

发明人： Zhang, Lintao ,  Yu, Yuan

IPC分类号： G06F17/11

CPC分类号： G06F17/504 ,  G06F17/11

摘要： Quantified Boolean formula (QBF) techniques are used in determining QBF satisfiability. A QBF is broken into component parts that are analyzable by a satisfiability (SAT) solver. Each component is then independently, and perhaps in parallel, analyzed for satisfiability. If a component is unsatisfiable, then it is determined that the QBF is unsatisfiable, and the analysis is stopped. If a component is satisfiable, then an assignment corresponding to the satisfiable component is noted. If a component is satisfiable, then it is appended to another untested component to provide a combination component, and the satisfiability of the combination component is analyzed. Such appending and analysis is repeated until the QBF is completed and determined to be satisfiable or determined to be unsatisfiable.

摘要翻译： 量化布尔公式（QBF）技术用于确定QBF可满足性。 QBF被分解成可满足性（SAT）求解器可分析的组件。 然后分析每个组件可以并行地分析可满足性。 如果组件不能令人满意，则确定QBF不能令人满意，并且分析停止。 如果组件是可满足的，则记录对应于可满足组件的分配。 如果组件满足，则将其附加到另一未测试组件以提供组合组件，并分析组合组件的可满足性。 这样的附加和分析被重复，直到QBF完成并确定为可满足或确定为不能令人满意。