摘要:
Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.
摘要:
A method for calculating a distance comprising receiving a map of an area converted as a first polygon; determining a plurality of vertices of the first polygon; determining a pair of the plurality of vertices that does not have an obstruction of the area intersecting a connecting line of the pair; generating a navigation mesh with the pair as a connecting line of the navigation mesh; and determining a distance between two points in the area using the navigation mesh.
摘要:
A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the hardware design to detect whether the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design cannot enter a livelock comprising the predetermined state.
摘要:
Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique.
摘要:
A distribution power flow analysis system and method are provided. A first relationship matrix and a second relationship matrix are used to analyze distribution power flow. The first relationship matrix is a relationship between a node injection current matrix and a branch current matrix. The second relationship matrix is a relationship between a node mismatch matrix and the branch current matrix. The system and method are applicable to cases of adding a new node, impedance or parallel loop. Compared with other conventional methods, the system and method have good robustness, fast execution speed and low memory space requirement in power flow calculation of a distribution power system.
摘要:
Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique.
摘要:
A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles.
摘要:
A counter example analysis support apparatus includes a counter example storage storing the counter example being a transition sequence of state and event that has not satisfied a verification condition as a result of the model checking; comprising: a related item list storage storing a related item list being a list associating a detection event, which is an event for detecting and generating the other-state, and a detected state, which is a state for determining the existence of the generation of the detection event; and a searching unit outputting a possible problem part from the counter example, wherein the searching unit determines whether a state included in the counter example is the detected state, and if the state included in the counter example is the detected state, determines whether a detection event corresponding to the related item list is generated before the detected state transits to a next state.