公开(公告)号：EP1899877A4

公开(公告)日：2011-12-28

申请号：EP06785706

申请日：2006-06-27

申请人： ARITHMOSYS INC

发明人： MUKUND SHRIDHAR ,  MITRA ANJAN

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

公开(公告)号：EP1899877A2

公开(公告)日：2008-03-19

申请号：EP06785706.0

申请日：2006-06-27

申请人： Arithmosys, Inc.

发明人： MUKUND, Shridhar ,  MITRA, Anjan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.