摘要:
A radio receiver (10) processes a carrier signal having a Doppler shifted frequency and carrying a coded signal having variable phase and amplitude. The coded signal is divided into a preamble portion and a message portion. A memory (23) stores samples of the coded signal representing at least some of the predetermined symbols of the preamble. A logic unit (16) divides the stored samples into a plurality of sample groups and identifies one sample group having the minimum variation of envelope amplitude. That sample group is used to provide additional samples by which the Doppler shift of the carrier frequency is estimated (70). The coded signal is delayed by a delay operation (100) and has its Doppler shift reduced. The Doppler reduced coded signal is processed by a filter operation (120) and a demodulator (130).
摘要:
Methods and apparatus for acquiring and verifying a code used by a base station. Acquisition time is reduced and circuitry simplified by performing Phase I (320) and Phase II (330) acquisitions in series, but in parallel with Phase III acquisition (340) and verification (350), which are done in series. Phase III code acquisition (340) is done by despreading the input signal using each of the possible codes in a code group. An estimation of the frequency offset between the base station and the terminal's local reference is used to correct the phase of the despread signals, which are coherently and non-coherently integrated. The largest accumulated value corresponds to the code used by the base station. The code is verified by despreading (380) the received signal, applying a frequency correction (360), and demodulating. The demodulated output is a series of symbols, and a count of these symbols verifies the acquired code.
摘要:
Pseudo-noise code modulated QPSK signals are correlated with a rotated version of the conjugate pseudo-noise code to lessen computational complexity. The rotation emulates a phase shift in the transmission channel, and the rotation is removed without computation by channel estimation.
摘要:
A modem for more efficiently processing a received analog signal into a digital output. The modem preferably features an adaptive equalizer with coefficients which are saved and reused for processing of subsequent analog signals, in order to reduce the time required to reach convergence. In addition, preferably the modem features an automatic carrier frequency control which adjusts the sampled digital signal according to both the carrier phase offset and the carrier frequency offset. Again, in order to process the signal more quickly and efficiently, preferably the carrier frequency offset is stored and reused for processing subsequent signals.
摘要:
A power calculator (19) calculates the power of an input signal in accordance with a component of an input received signal (I, Q). A comparator (20) asserts an unmodulated signal detection signal when the power calculated by the power calculator exceeds a prescribed threshold. A maximum value detector (41) detects the maximum power of the input received signal in accordance with the assertion of the unmodulated signal detection signal and generates non-modulated signal position instruction information with a maximum value detection signal, and a frequency error calculator (42; 42, 50, 60, 70) calculates an error of a carrier frequency on the basis of the received signal corresponding to the maximum power. The frequency error is calculated only with a non-modulated signal, whereby the frequency error can be correctly calculated and the non-modulated signal position can also be correctly detected.
摘要:
A block phase estimator (102) includes a phase averaging circuit (80). A first embodiment of the phase averaging circuit (80) includes a phase differencing circuit (82) coupled to an averager input (80), a first modulo circuit (84) coupled to the phase differencing circuit (82), a filter (86) coupled to the first modulo circuit (86), and a summation circuit (88) having a positive input and a negative input, the positive input being coupled to the averager input (80), the negative input being coupled to the filter (86). The phase averaging circuit (80) further includes a second modulo circuit (89) coupled to the summation circuit (88). An alternative embodiment of the phase averaging circuit (fig. 11) includes a delay line (112) having a plurality of taps (114) coupled to an averager input (116) and a plurality of first subtractor circuits (118), a first input of each first subtractor circuit (118) being coupled to the averager input (116), a second input of each first subtractor circuit (118) being coupled to a corresponding tap (114) of the plurality of taps (114).
摘要:
The timing of a carrier signal is tracked in a receiver. The receiver receives a signal produced by a transmitter having a single frequency source which is used to generate a reference clock frequency and a carrier signal frequency, there being a fixed, predetermined relationship between the reference and carrier frequencies. In the receiver there is a single frequency source which is used to generate a reference clock frequency and a carrier reference signal frequency, there being a fixed, predetermined relationship between the reference and carrier reference frequencies. The fixed, predetermined relationship in the transmitter and the receiver is the same.