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    ULTRA LOW POWER WIDEBAND ASYNCHRONOUS BINARY PHASE SHIFT KEYING DEMODULATION CIRCUIT USING FIRST ORDER SIDEBAND FILTERS ALIGNED AT ZERO DEGREE PHASE
    1.
    发明公开
    ULTRA LOW POWER WIDEBAND ASYNCHRONOUS BINARY PHASE SHIFT KEYING DEMODULATION CIRCUIT USING FIRST ORDER SIDEBAND FILTERS ALIGNED AT ZERO DEGREE PHASE 审中-公开
    超低功率宽带异步二值相移键控解调电路采用一阶边带滤波器在零相位调整

    公开(公告)号：EP3188428A2

    公开(公告)日：2017-07-05

    申请号：EP15836598.1

    申请日：2015-08-24

    申请人： Wilkerson, Benjamin P.

    发明人： Wilkerson, Benjamin P.

    IPC分类号： H04L27/233

    CPC分类号： H04L27/2331 ,  H04B1/71637 ,  H04B2201/71636 ,  H04L7/0278 ,  H04L27/0014 ,  H04L27/2334 ,  H04L27/2335 ,  H04L2027/0036

    摘要： An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. Provided is an ultra low power wideband asynchronous BPSK demodulation circuit configured by comprising: a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter of which a cutoff frequency is a carrier frequency, so as to output an analog signal delayed by a ¼ period of the carrier frequency from an upper sideband analog signal, and a lower sideband analog signal; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0°, that is, an analog pulse signal indicated according to a phase shift part of a BPSK modulation signal, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.

    摘要翻译： 本发明的一个实施例涉及超低功率宽带异步二进制相移键控（BPSK）解调方法及其电路配置。 提供一种超低功率宽带异步BPSK解调电路，包括：边带分割和上边带信号延迟单元，通过一阶高通滤波器和一阶低通滤波器将调制信号分成上边带和下边带， 其截止频率为载波频率，以从上边带模拟信号和下边带模拟信号输出延迟了载波频率的1/4周期的模拟信号; 数据解调单元通过迟滞电路锁存由延迟的上边带模拟信号和下边带模拟信号之间的相位差在0°排列的模拟信号之间的差异所产生的信号，即，模拟信号 根据BPSK调制信号的相移部分指示脉冲信号，以解调数字数据; 以及数据时钟恢复单元，用于通过使用通过比较器和数据信号从下边带模拟信号数字化的信号来生成数据时钟。

    End of communication detection
    2.
    发明公开
    End of communication detection 审中-公开
    Ende des Kommunikationsnachweises

    公开(公告)号：EP2887270A1

    公开(公告)日：2015-06-24

    申请号：EP14193023.0

    申请日：2014-11-13

    申请人： NXP B.V.

    发明人： van de Beek, Remco ,  Ciacci, Massimo ,  Al-Kadi, Ghiath

    IPC分类号： G06K19/067 ,  H04L7/04 ,  H04L27/227 ,  H04B5/00

    CPC分类号： H04L1/0039 ,  G06K19/067 ,  H04B5/0031 ,  H04B5/0062 ,  H04B5/0093 ,  H04L5/001 ,  H04L7/041 ,  H04L7/042 ,  H04L27/22 ,  H04L27/227 ,  H04L27/2272 ,  H04L27/2273 ,  H04L2027/0036 ,  H04L2027/0057 ,  H04L2027/0095

    摘要： An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.

    摘要翻译： 公开了一种用于检测通信结束的装置。 该装置包括用于接收编码信号的接口电路和耦合到接口电路的输出的载波信号恢复电路。 载波信号恢复电路被配置为输出编码信号的载波信号和与载波信号异相的第二信号。 该装置还包括解码电路，其被配置为根据由载波信号恢复电路输出的编码信号和载波信号的二进制编码信号进行解码。 该装置还包括检测电路，其被配置为根据编码信号和第二信号检测编码信号中的通信结束的指示。

    4th order phase tracking for DPSK receivers
    8.
    发明公开
    4th order phase tracking for DPSK receivers 审中-公开
    相位滞后第四为了DPSK接收机

    公开(公告)号：EP1213890A3

    公开(公告)日：2005-08-24

    申请号：EP01128477.5

    申请日：2001-12-06

    申请人： NORTHROP GRUMMAN CORPORATION

    发明人： Myers, Michael H.

    IPC分类号： H04L27/22

    CPC分类号： H04L27/22 ,  H04L2027/0036 ,  H04L2027/0046

    摘要： A system for and a method of demodulating a received VHF radio frequency signal, for example on an aircraft, the radio frequency signal including a baseband signal with differential phase shift keying encoded data, to obtain the encoded data. The signal is received by a signal receiver (20), and a symbol tracking select value is determined in a symbol synchronization circuit (22). Doppler error in the received signal is estimated in a Doppler estimator (24). The received signal, the symbol tracking select value, and the estimated Doppler error are applied to a symbol demodulator (32) within which the received signal is multiplied in a multiplier (42) to remove that Doppler error. The resulting signal is filtered and decimated by a decimating low pass filter (48) and normalized by a signal generator (52) which generates the arctangent of the in-phase and quadrature components of the baseband signal. This arctangent signal is multiplied in a multiplier (54) by a constant equal to the phase order of the signal to strip off the phase angle modulation. The resulting signal is applied through two second order phase lock loops (60,74) in tandem to remove all derivatives of the input phase signal. The arctangent of the resulting signal is generated in a signal generator (80), and the resulting angles are mapped in a nearest neighbor map circuit (82). The difference between successive angles is determined by a difference circuit (84) to compute the differential phase, and the resulting signal is applied to a gray code to binary mapping circuit (86) which detects the encoded data. This data is applied to message processing and utilizing circuits (34) for utilization in accordance with its information content.