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    Method and apparatus for avoiding spurs in chip
    2.
    发明授权
    Method and apparatus for avoiding spurs in chip 有权

    公开(公告)号：EP2849363B1

    公开(公告)日：2018-06-13

    申请号：EP13306263.8

    申请日：2013-09-16

    申请人： ST-Ericsson SA

    发明人： Pineau, Stéphane ,  Harnay, Didier ,  Sittler, François

    IPC分类号： H04B15/04

    CPC分类号： H03L7/1075 ,  H03L7/0802 ,  H04B15/04

    摘要： A method of rejecting spurs within a chip containing analog and digital functions, the spurs being timed by an associated clock signal derived from the output signal of a High Frequency, HF, fractional Phase Locked Loop, PLL, the method comprising: - determining original analog rejection bandwidths associated with the operation of analog functions; - identifying original spurs associated with the operation of the digital functions and capable of affecting the original analog rejection bandwidths directly or indirectly; - obtaining a final analog rejection bandwidth based on the original analog rejection bandwidths; - obtaining final spurs based on the original spurs; - determining a frequency shift of the output frequency of the HF fractional PLL adapted to reject the final spurs from the final analog rejection bandwidth; and, - controlling the HF fractional PLL to shift the output frequency of said HF fractional PLL by the frequency shift.

    SYSTEM AND METHOD OF CONTROLLING POWER CONSUMPTION IN A DIGITAL PHASE LOCKED LOOP (DPLL)
    7.
    发明公开
    SYSTEM AND METHOD OF CONTROLLING POWER CONSUMPTION IN A DIGITAL PHASE LOCKED LOOP (DPLL) 有权
    系统和方法用于控制电力用在数字锁相环（DPLL）

    公开(公告)号：EP2286514A1

    公开(公告)日：2011-02-23

    申请号：EP09739682.4

    申请日：2009-04-29

    申请人： QUALCOMM Incorporated

    发明人： SUN, Bo ,  BALLANTYNE, Gary, John ,  SAHOTA, Gurkanwal, Singh

    IPC分类号： H03L7/00 ,  H03L7/08

    CPC分类号： H03L7/00 ,  H03L7/0802 ,  H03L2207/50

    摘要： An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.

    Frequency synthesiser
    8.
    发明公开
    Frequency synthesiser 有权
    频率合成器

    公开(公告)号：EP2237418A2

    公开(公告)日：2010-10-06

    申请号：EP09251261.5

    申请日：2009-05-06

    申请人： NXP B.V.

    发明人： Drago, Salvatore ,  Sebastiano, Fabio ,  Leenaerts, Domine ,  Breems, Lucien ,  Nauta, Bram

    IPC分类号： H03K3/03 ,  H03L7/08 ,  H03K3/012

    CPC分类号： H03K3/0322 ,  H03K3/012 ,  H03L7/0802 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06 ,  H03L2207/50

    摘要： A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising:
    a digital controlled oscillator (33) configured to generate an output signal (F o ) having a frequency controlled by an input digital control word (DCW);
    a feedback loop (35-38) connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and
    a duty cycle module (32) connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

    摘要翻译： 一种用于无线电收发信机的低功率频率合成器电路（30），所述合成器电路包括：数字控制振荡器（33），被配置为生成具有由输入数字控制字（DCW）控制的频率的输出信号（Fo）; 一个连接在数字控制振荡器的输出端和输入端之间的反馈回路（35-38），反馈回路被配置为根据从输入频率控制字导出的误差将数字控制字提供给数字控制振荡器的输入端（ FCW）和输出信号; 和连接到所述数字控制振荡器和所述反馈回路的占空比模块（32），所述占空比模块被配置为生成多个控制信号以周期性地启用和禁用所述数字控制振荡器达到输入的时钟周期的设定分数 参考时钟信号（RefClock）。