利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

574 条记录 (耗时 0.018 秒)

    METHOD AND DECODER FOR PROCESSING A DIGITAL VIDEO SIGNAL
    1.
    发明授权
    METHOD AND DECODER FOR PROCESSING A DIGITAL VIDEO SIGNAL 有权
    方法和解码器，用于处理一个数字视频

    公开(公告)号：EP1402736B1

    公开(公告)日：2006-03-08

    申请号：EP02735834.0

    申请日：2002-06-13

    申请人： Koninklijke Philips Electronics N.V.

    发明人： DEL CORSO, Sandra

    IPC分类号： H04N7/26

    CPC分类号： H04N19/80 ,  H04N5/144 ,  H04N5/21 ,  H04N19/186 ,  H04N19/503

    摘要： The present invention relates to a method and a decoder for processing a digital video signal, said video signal representing a sequence of images. It is characterized in that it comprises the steps of:- detecting motion pixels in a current image (I(t)),- median filtering a transformed block (Bc) of the current image through a sub-step of spatial median filtering a first set of coefficients (Mcs, Mu, Md) and a sub-step of temporal median filtering a second set of coefficients (Mct, Mp, Mn), - computing an inverse transformed block from the filtered block, and- replacing pixels in the inverse transformed block by said detected motion pixels.

    CLOCK DOMAIN CROSSING FIFO
    8.
    发明公开
    CLOCK DOMAIN CROSSING FIFO 有权
    FIFO过渡中风地区

    公开(公告)号：EP1442550A2

    公开(公告)日：2004-08-04

    申请号：EP02772679.3

    申请日：2002-10-02

    申请人： Koninklijke Philips Electronics N.V.

    发明人： PONTIUS, Timothy, A. ,  PAYNE, Robert, L. ,  EVOY, David, R.

    IPC分类号： H04L7/02 ,  G06F5/06 ,  G06F1/04

    CPC分类号： H04L7/02 ,  G06F5/10 ,  G06F2205/102 ,  H04L7/0008 ,  H04L7/005

    摘要： A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.