公开(公告)号：EP2571052A4

公开(公告)日：2017-04-19

申请号：EP10851389

申请日：2010-05-12

Applicant: RENESAS ELECTRONICS CORP

Inventor： FUJISAWA ATSUSHI

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00012 ,  H01L2924/01014 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/45015 ,  H01L2924/207

公开(公告)号：EP2768015A1

公开(公告)日：2014-08-20

申请号：EP13799475.2

申请日：2013-08-02

Applicant: Huawei Technologies Co., Ltd.

Inventor： YUN, Lungang ,  HUANG, An ,  TIAN, Pengbo

IPC: H01L21/58 ,  H01L23/48

CPC classification number: H01L24/83 ,  H01L23/66 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05638 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/1411 ,  H01L2224/2733 ,  H01L2224/29019 ,  H01L2224/29078 ,  H01L2224/29082 ,  H01L2224/29144 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83444 ,  H01L2224/83805 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/1421 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01014

Abstract: Relating to electronic components, the present invention provides a method for welding a gold-silicon eutectic chip, and a transistor, to resolve a technical problem in a current gold-silicon eutectic welding method that a cost of a transistor increases because a gold layer electroplated on a chip carrier is relatively thick. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present invention reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor.

Abstract translation: 关于电子元件，本发明提供了一种用于焊接金 - 硅共晶芯片和晶体管的方法，以解决目前的金 - 硅共晶焊接方法中的技术问题，即由于镀金层，晶体管的成本增加 芯片上的载体比较厚。 用于焊接金 - 硅共晶芯片的方法包括：在芯片载体的表面上电镀厚度小于或等于1微米的金层; 在焊接区域的金层上粘合多个金突起; 并且在共晶温度下在焊接区域中摩擦芯片以形成焊接层。 晶体管包括芯片，芯片载体和连接芯片和芯片载体的中间层，其中焊接中间层是通过使用上述焊接方法获得的焊接层。 本发明可以减少金的使用量，同时降低金 - 硅共晶焊接的成本，从而降低晶体管的成本。

公开(公告)号：EP2652782A2

公开(公告)日：2013-10-23

申请号：EP11805336.2

申请日：2011-12-14

Applicant: Tessera, Inc.

Inventor： OGANESIAN, Vage ,  HABA, Belgacem ,  MOHAMMED, Ilyas ,  SAVALIA, Piyush ,  MITCHELL, Craig

IPC: H01L21/98

CPC classification number: H01L23/562 ,  B81C1/00269 ,  B81C1/00357 ,  H01L21/2007 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/13 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83345 ,  H01L2224/83385 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/1027 ,  H01L2924/1032 ,  H01L2924/1037 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2924/00

Abstract: A method of bonding first and second microelectronic elements includes pressing together a first substrate 100 containing active circuit elements 108 therein with a second substrate 112, with a flowable dielectric material 102 between confronting surfaces of the respective substrates, each of the first and second substrates 100,112 having a coefficient of thermal expansion less than 10 parts per million/ °C, at least one of the confronting surfaces having a plurality of channels 118A-118F extending from an edge of such surface, such that the dielectric material 102 between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material 102 flows into at least some of the channels.

公开(公告)号：EP2571052A1

公开(公告)日：2013-03-20

申请号：EP10851389.6

申请日：2010-05-12

Applicant: Renesas Electronics Corporation

Inventor： FUJISAWA, Atsushi

IPC: H01L23/50

CPC classification number: H01L23/49568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00012 ,  H01L2924/01014 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A trench portion (trench) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.

Abstract translation: 沟槽部分（沟槽）形成在具有比包括在半导体器件中的管芯焊盘的外形尺寸小的四边形平面形状的芯片键合区域的四个角部中的每一个处。 每个沟槽沿与连接排列沟槽部分的角部之间的对角线交叉的方向形成，并且每个沟槽部分的两端延伸到芯片结合区域的外部。 半导体芯片被安装在芯片结合区域上以插入管芯结合材料。 以此方式，可以抑制在将半导体器件安装在安装基板上时在回流步骤中剥离芯片​​接合材料。 而且，即使发生剥离，也可以抑制剥离的扩大。

公开(公告)号：EP2161739A4

公开(公告)日：2010-08-25

申请号：EP07860422

申请日：2007-12-27

Applicant: SUMITOMO BAKELITE CO

Inventor： YOSHIDA MASATO

IPC: H01L21/52 ,  C09J7/00 ,  C09J11/06 ,  C09J133/00 ,  C09J163/00 ,  H01L23/29 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: C08G59/621 ,  C08L33/00 ,  C08L2666/04 ,  C08L2666/14 ,  C09J133/00 ,  C09J163/00 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/181 ,  Y10T428/31515 ,  H01L2924/0635 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The adhesive film of the present invention is adapted to be used for bonding a semiconductor element and a substrate together or bonding semiconductor elements together. The adhesive film is formed of a resin composition containing an epoxy resin, an acrylic resin, and an acrylic oligomer having a weight average molecular weight of 6,000 or less. The resin composition is characterized in that in the case where an amount of the acrylic resin contained in the resin composition is defined as Wa and an amount of the acrylic oligomer contained therein is defined as Wb, a ratio of Wa/Wb is in the range of 0.5 to 4. Further, the semiconductor device of the present invention is characterized in that a semiconductor element and a substrate or semiconductor elements are bonded together using the above mentioned adhesive film.

公开(公告)号：EP1972010A2

公开(公告)日：2008-09-24

申请号：EP07717691.5

申请日：2007-01-05

Applicant: INTERNATIONAL RECTIFIER CORPORATION

Inventor： HAUENSTEIN, Henning

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/39 ,  H01L24/83 ,  H01L2224/29111 ,  H01L2224/32057 ,  H01L2224/32503 ,  H01L2224/73153 ,  H01L2224/83101 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15747 ,  H01L2924/18301 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/29099

Abstract: A substrate on which a silicon device is mounted includes a plurality of protrusions extending upward from a top surface of the substrate and a solder layer formed on the top of the substrate such that the plurality of protrusions extends through the solder layer and a top portion of each protrusion of the plurality of protrusions is stamped down to be level with a top surface of the solder layer such that the silicon device is supported on the plurality of protrusions when placed on the substrate. The protrusions are preferably gouged up from the surface of the substrate with a needle like tool. A stamper tool is used to stamp the protrusions down to their desired height such that they are properly positioned to support the silicon device. The solder layer may be a solder pre-form or may be a layer of solder paste.

公开(公告)号：EP0913429B1

公开(公告)日：2005-12-28

申请号：EP98308849.3

申请日：1998-10-29

Applicant: Hitachi Chemical Company, Ltd.

Inventor： Takeuchi, Kazumasa ,  Saito, Tetsuya ,  Nanaumi, Ken

IPC: C08L79/08 ,  C08L63/00 ,  C09J179/08 ,  C09J163/08 ,  H01L23/498 ,  H01L21/48

CPC classification number: B32B15/08 ,  B32B3/266 ,  B32B7/12 ,  B32B15/20 ,  B32B2311/12 ,  B32B2323/10 ,  B32B2327/18 ,  B32B2367/00 ,  B32B2379/08 ,  B32B2457/00 ,  C08G18/3243 ,  C08G18/345 ,  C08G18/61 ,  C08G77/388 ,  C08G77/452 ,  C08L63/00 ,  C08L79/08 ,  C08L83/00 ,  C08L2666/14 ,  C08L2666/20 ,  C09D183/10 ,  C09J7/22 ,  C09J7/35 ,  C09J179/08 ,  C09J183/10 ,  C09J2479/08 ,  C09J2479/086 ,  H01L23/293 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K2201/0154 ,  Y10T156/1052 ,  Y10T428/12361 ,  Y10T428/12493 ,  Y10T428/12514 ,  Y10T428/12569 ,  Y10T428/12889 ,  Y10T428/12903 ,  Y10T428/24273 ,  Y10T428/24331 ,  Y10T428/31663 ,  Y10T428/31667 ,  H01L2924/0715 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An adhesive sheet comprises a polyimide base layer and an adhesive layer (a) disposed on at least one side of the polyimide base layer, the adhesive layer (a) being a layer of a B-stage cured product of a siloxane-modified polyamideimide resin composition comprising 100 parts by weight of a siloxane-modified polyamideimide resin and 1 to 200 parts by weight of a thermosetting resin ingredient. A chip-size package board is produced by making a through-hole in the adhesive sheet, laminating a copper foil on the adhesive layer (a), forming a circuit by removing unnecessary parts of the copper foil by etching, and then gold plating a surface of the circuit. A semiconductor device is prepared by bonding a semiconductor chip to the surface of the chip-size package board bearing the circuit, connecting the circuit of the chip-size package board to bonding pads of the semiconductor chip, and sealing the circuit of the chip-size package board, the bonding wires and the semiconductor chip with a molded resin.

公开(公告)号：EP1213754A3

公开(公告)日：2005-05-25

申请号：EP02003791.7

申请日：1995-03-17

Applicant: HITACHI CHEMICAL CO., LTD.

Inventor： Fukutomi, Naoki ,  Tsubomatsu, Yoshiaki ,  Inoue, Fumio ,  Yamazahki, Toshio ,  Ohhata, Hirohito ,  Hagiwara, Shinsuke ,  Taguchi, Noriyuki ,  Nomura, Hiroshi

IPC: H01L21/68 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L21/568 ,  H01L21/4803 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83102 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/203 ,  H01L2924/351 ,  H05K3/20 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/0002

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract translation: 提供了半导体封装基板，可以满足向半导体集成度高的趋势。 将镍层电镀在电镀铜箔上以形成布线图案。 将LSI芯片安装在铜箔上，通过引线接合连接LSI芯片和布线图案的端子，然后用半导体密封型环氧树脂密封。 只有铜箔用碱蚀刻剂溶解掉才能暴露镍。 对于具有低铜溶力的镍剥离器，去除镍层以露出布线图案。 涂覆阻焊剂，并且以使得连接端子部分露出的方式形成图案。 将焊球放置在布线图案的露出部分，然后熔合。 布线图案通过焊球与外部印刷电路板连接。

公开(公告)号：EP1261028A3

公开(公告)日：2005-05-11

申请号：EP02011192.8

申请日：2002-05-21

Applicant: Hitachi, Ltd.

Inventor： Hasebe, Takehiko, Hitachi, Ltd., Intl.Prop. Group ,  Yokozuka, Takehide, Hitachi,Ltd., Intl.Prop. Group ,  Ushifusa, Nobuyuki, Hitachi,Ltd., Intl.Prop. Group ,  Harada, Masahide, Hitachi,Ltd., Intl.Prop. Group ,  Matsuzaki, Eiji, Hitachi,Ltd., Intl.Prop. Group ,  Hozoji, Hiroshi, Hitachi,Ltd., Intl.Prop. Group

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/32057 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/83851 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/021 ,  H05K1/056 ,  H05K1/144 ,  H05K3/384 ,  H05K3/4608 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10734 ,  H01L2924/05432 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides an electronic apparatus having a metal core substrate including a metal plate (101), an insulating layer formed on the metal plate and a conductive layer formed on the insulating layer, and an electronic part, and to which the conductive layer and a terminal of the electronic part are connected. In the electronic apparatus, a member having a high thermal conductivity is arranged so as to be in contact with both of the metal plate and the electronic part. Accordingly, a heat radiating property of the electronic apparatus is increased.

公开(公告)号：EP1195813A3

公开(公告)日：2005-01-05

申请号：EP01302542.4

申请日：2001-03-20

Applicant: Sanyo Electric Co., Ltd.

Inventor： Sakamoto, Noriaki ,  Kobayashi, Yoshiyuki ,  Sakamoto, Junji ,  Okada, Yukio ,  Igarashi, Yusuke ,  Maehara, Eiju ,  Takahashi, Kouji

IPC: H01L23/367 ,  H01L23/433 ,  H01L23/31 ,  H01L21/68

CPC classification number: H01L24/32 ,  G11B5/4853 ,  H01L21/4832 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68377 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/182 ,  H05K1/189 ,  H05K2201/10416 ,  H05K2201/10727 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01046 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to the heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).