MEMS SENSOR DEVICES HAVING A SELF-TEST MODE

    公开(公告)号:EP3112880B1

    公开(公告)日:2018-06-20

    申请号:EP16176950.0

    申请日:2016-06-29

    申请人: NXP USA, Inc.

    IPC分类号: G01P21/00 G01L25/00

    CPC分类号: G01P21/00 G01P15/125

    摘要: A micro-electro-mechanical system (MEMS) device comprises a micro-electro-mechanical system (MEMS) sensor; a detector circuit; a controller circuit coupled with the MEMS sensor; a first connection arranged between a first output of the MEMS sensor and a first input of the detector circuit; a second connection arranged between a second output of the MEMS sensor and a second input of the detector circuit; and a first switch arranged in the first connection. The controller circuit is configured to open the first switch during a first test mode so as to connect only a single input of the detector circuit with an output of the MEMS sensor. A further switch may be provided to connect two outputs of the MEMS sensor to a single input of the detector circuit.

    A delay line phase shifter with selectable phase shift

    公开(公告)号:EP2621087B1

    公开(公告)日:2018-06-13

    申请号:EP13151793.0

    申请日:2013-01-18

    申请人: NXP USA, Inc.

    IPC分类号: H03H7/20

    CPC分类号: H03H7/20

    摘要: A phase shifter (101) with selectable phase shift comprises a switchable phase shifting element (107, 109, 111, 113) that includes a first and second signal path (115, 119) coupled between an input (103) and an output (117) and providing a, respective, first and second phase shift for a signal coupled through the respective signal paths; a switch circuit (121) for selecting between the first and second signal paths where the first and second signal paths and the switch circuit are configured to equalize the insertion loss for the first and second signal path, the phase shifter further including control circuit (123) for controlling the switch circuit.

    SYSTEM AND METHOD FOR CLOCK SIGNAL GENERATION
    5.
    发明授权
    SYSTEM AND METHOD FOR CLOCK SIGNAL GENERATION 有权
    用于时钟信号发生的系统和方法

    公开(公告)号:EP2700171B1

    公开(公告)日:2018-04-04

    申请号:EP11863964.0

    申请日:2011-04-20

    申请人: NXP USA, Inc.

    发明人: BODE, Hubert

    IPC分类号: H03L7/183 H03L7/099

    CPC分类号: H03L7/08 H03L7/183 H03L7/1974

    摘要: A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal.

    Synchronous rectifier timer for discontinuous mode DC/DC converter
    6.
    发明公开
    Synchronous rectifier timer for discontinuous mode DC/DC converter 审中-公开
    用于非连续模式DC / DC转换器的同步整流器定时器

    公开(公告)号:EP2677647A3

    公开(公告)日:2018-02-28

    申请号:EP13169583.5

    申请日:2013-05-28

    申请人: NXP USA, Inc.

    IPC分类号: H02M3/158 H02M1/00 H02M3/156

    摘要: A DC-DC converter (100) includes a switching transistor (M0) connecting an input power terminal (VIN) to an inductor (114) that is also connected to an output power terminal (VOUT), a synchronous rectification transistor (M1) connected to a junction node (113) between the inductor (114) and the switching transistor (M0), and a synchronous rectifier control circuit (200) with an integration capacitor (226) having a voltage that is charged and discharged by first and second current sources (210, 220) to track the charging and discharging of the inductor current, thereby generating a synchronous rectifier control signal (SR) that is applied to the synchronous rectification transistor to discharge the inductor current to zero.

    摘要翻译: DC-DC转换器(100)包括将输入电源端子(VIN)连接到也连接到输出电源端子(VOUT)的电感器(114)的开关晶体管(M0),连接到同步整流晶体管 (114)和开关晶体管(M0)之间的结点(113)以及具有积分电容器(226)的同步整流器控制电路(200),所述积分电容器具有通过第一和第二电流充电和放电的电压 源(210,220)以跟踪电感器电流的充电和放电,由此生成同步整流器控制信号(SR),该同步整流器控制信号(SR)被施加到同步整流晶体管以将电感器电流放电至零。

    Pressure sensor with differential capacitive output
    7.
    发明授权
    Pressure sensor with differential capacitive output 有权
    带差分电容输出的压力传感器

    公开(公告)号:EP2703799B1

    公开(公告)日:2018-02-14

    申请号:EP13179577.5

    申请日:2013-08-07

    申请人: NXP USA, Inc.

    IPC分类号: B60C23/04 G01L9/12 G01L9/00

    摘要: A MEMS pressure sensor device (200, 400, 500, 600) is provided that can provide both a linear output with regard to external pressure, and a differential capacitance output so as to improve the signal amplitude level. These benefits are provided through use of a rotating proof mass (250, 420, 520) that generates capacitive output (283, 293) from electrodes configured at both ends of the rotating proof mass. Sensor output can then be generated using a difference between the capacitances generated from the ends of the rotating proof mass. An additional benefit of such a configuration is that the differential capacitance output changes in a more linear fashion with respect to external pressure changes than does a capacitive output from traditional MEMS pressure sensors.

    ELECTRONIC CIRCUIT, SAFETY CRITICAL SYSTEM, AND METHOD FOR PROVIDING A RESET SIGNAL
    8.
    发明授权
    ELECTRONIC CIRCUIT, SAFETY CRITICAL SYSTEM, AND METHOD FOR PROVIDING A RESET SIGNAL 有权
    电子电路,安全临界系统和提供复位信号的方法

    公开(公告)号:EP2596412B1

    公开(公告)日:2018-01-03

    申请号:EP10854978.3

    申请日:2010-07-20

    申请人: NXP USA, Inc.

    IPC分类号: G06F1/24 G06F1/04

    CPC分类号: H03L7/00 G06F1/24

    摘要: An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.

    SWITCHED CURRENT CONTROL MODULE AND METHOD THEREFOR
    9.
    发明公开
    SWITCHED CURRENT CONTROL MODULE AND METHOD THEREFOR 审中-公开
    开关电流控制模块及其方法

    公开(公告)号:EP3261241A1

    公开(公告)日:2017-12-27

    申请号:EP16305746.6

    申请日:2016-06-20

    申请人: NXP USA, Inc.

    IPC分类号: H02M3/156

    摘要: A switched current control module comprises a hysteretic control component arranged to receive high and low threshold values and an indication of a current flow through a load, and to output a switched current control signal based on a comparison of the current flow indication to the high and low threshold values. A threshold generator is arranged to generate the high and low threshold values based on a base threshold value and a hysteretic excursion value. A base threshold value generator is arranged to generate the base threshold value based on the current flow indication and a setpoint value. A hysteretic excursion value generator is arranged to receive an indication of a switching frequency of the switched current control signal output by the hysteretic control component, and to generate the hysteretic excursion value based on the indicated switching frequency of the switched current control signal.

    摘要翻译: 开关电流控制模块包括滞后控制部件,该滞后控制部件布置成接收高阈值和低阈值以及通过负载的电流的指示,并且基于电流指示与高的比较来输出开关电流控制信号,并且 低阈值。 阈值生成器被布置为基于基准阈值和滞后偏移值生成高阈值和低阈值。 基准阈值生成器被布置为基于当前流量指示和设定点值来生成基准阈值。 滞后偏移值生成器被布置为接收由滞后控制部件输出的开关电流控制信号的开关频率的指示,并且基于所指示的开关电流控制信号的开关频率生成滞后偏移值。

    SYSTEM, ENCODER AND DECODER FOR VERIFICATION OF IMAGE SEQUENCES
    10.
    发明公开
    SYSTEM, ENCODER AND DECODER FOR VERIFICATION OF IMAGE SEQUENCES 审中-公开
    用于验证图像序列的系统,编码器和解码器

    公开(公告)号:EP3244622A1

    公开(公告)日:2017-11-15

    申请号:EP16168904.7

    申请日:2016-05-10

    申请人: NXP USA, Inc.

    摘要: The present application relates to a system for verifying integrity of a stream of image frames including an encoder logic module and a decoder logic module. On source side, a test line insertion logic module receiving the stream is arranged upstream to the encoder logic module encoding the stream. The test line insertion logic module is configured to include one or more test lines into the image frames. A color coding is assigned to the one or more test lines. The color coding is selected from a coding scheme. On destination side, a test line detection and extraction logic module is arranged downstream to the decoder logic module receiving the encoded stream. The test line detection and extraction logic module extracts the color coding from the received image frames and verifies extracted coding data against the coding scheme. The coding data comprises at least the extracted color coding.

    摘要翻译: 本申请涉及用于验证图像帧流的完整性的系统,其包括编码器逻辑模块和解码器逻辑模块。 在源端,接收流的测试线插入逻辑模块被布置在编码流的编码器逻辑模块的上游。 测试线插入逻辑模块被配置为将一个或多个测试线包括到图像帧中。 彩色编码被分配给一个或多个测试线。 颜色编码从编码方案中选择。 在目的地侧,测试线检测和提取逻辑模块被布置在接收编码流的解码器逻辑模块的下游。 测试线检测和提取逻辑模块从接收的图像帧中提取颜色编码,并根据编码方案验证所提取的编码数据。 编码数据至少包括提取的颜色编码。