摘要:
Embodiments of an invention for loading and virtualizing cryptographic keys are disclosed. In one embodiment, a processor includes a local key storage location, a backup key storage location, and execution hardware. Neither the local key storage location nor the backup key storage location is readable by software. The execution hardware is to perform a first operation and a second operation. The first operation includes loading a cryptographic key into the local key storage location. The second operation includes copying the cryptographic key from the local key storage location to the backup key storage location.
摘要:
In one embodiment, a bandwidth management controller is coupled to a debug interconnect to dynamically allocate buffer space of a plurality of data buffers to hardware trace information, software trace information, and firmware trace information. The bandwidth management controller further includes a control logic to dynamically control at least one of a voltage and a frequency of the debug interconnect based at least in part on a debug activity level or a functional activity level. Other embodiments are described and claimed.
摘要:
An apparatus and method for performing a spin-loop jump. One embodiment of a processor comprises: jump-pause execution logic to execute a jump-pause instruction, the jump-pause instruction to specify a condition and identify a destination instruction; wherein responsive to the execution of the jump-pause instruction, the jump-pause execution logic is to provide a hint that a loop between the jump-pause instruction and the destination instruction comprises a spin-wait loop and to test the condition, the jump-pause execution logic to delay execution by a specified amount prior to jumping to the destination instruction if the condition is satisfied. A second embodiment of a processor comprisies test-subtract execution logic to execute a test-subtract instruction, the test-subtract instruction to decrement the counter value in a second source register, the test-subtract execution logic to further test the monitored value in a first source register or memory and the counter value in the second source register, wherein the test-subtract execution logic is to exit a spin-wait loop if the monitored value has a value indicating an exit condition or if the counter value is equal to zero.
摘要:
Apparatuses, methods and storage medium associated with provision and receipt of virtual sensor service, are disclosed. In embodiments, an apparatus may comprise a virtual sensor server configured to provide virtual sensor service to one or more mobile client devices to virtualize one or more sensors of each of the one or more mobile client devices. Virtualization of the one or more sensors of each of the one or more mobile client devices may comprise provision of sensor data to each of the one or more mobile client devices, or reporting of sensor data to one or more recipients external to the one or more mobile client devices on behalf of respective one or ones of the one or more mobile client devices. The provision or the reporting supersedes the corresponding sensor on the respective one or more of the mobile client devices. Other embodiments may be described and/or claimed.
摘要:
Described is a method for assigning hall calls comprising the steps of receiving a hall call signal, receiving information regarding an elevator system, assigning a destination to the hall call signal, and calculating a call cost value for each elevator car using a handling capacity coefficient. The controller designates the elevator with the lowest call cost value to respond to a call signal. The handling capacity coefficient is a value that reflects the current traffic conditions of an elevator system.
摘要:
An apparatus for compressing holographic data includes an image capture device for capturing an image of an interference pattern reconstructed by irradiating a reference beam and converting the image into m bits. In such an apparatus, a splitter removes least significant j bits from the m-bit data and divides m-j bits of the m-bit data into most significant k bits and remaining m-j-k bits. Thereafter, a compressor converts the most significant k bits into 1 bits, which is combined with the m-j-k bits to output n bits, wherein 1