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    Method of making a logic transistor and a non-volatile memory (nvm) cell
    5.
    发明授权
    Method of making a logic transistor and a non-volatile memory (nvm) cell 有权
    制造逻辑晶体管和非易失性存储器（nvm）单元的方法

    公开(公告)号：EP2725607B1

    公开(公告)日：2017-12-13

    申请号：EP13188538.6

    申请日：2013-10-14

    申请人： NXP USA, Inc.

    发明人： Shroff, Mehul ,  Hall, Mark D

    IPC分类号： H01L21/8239 ,  H01L27/105

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/66545

    摘要： An oxide-containing layer (18) is formed directly on a semiconductor layer (12) in an NVM region (14), and a first partial layer (20) of a first material is formed over the oxide-containing layer in the NVM region. A first high-K dielectric layer (22) is formed directly on the semiconductor layer in a logic region (16). A first conductive layer (24) is formed over the first dielectric layer in the logic region. A second partial layer (26) of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer (28) if the cell is a floating gate cell or a select gate (28) if the cell is a split gate cell.

    Method of making a logic transistor and a non-volatile memory (nvm) cell
    6.
    发明公开
    Method of making a logic transistor and a non-volatile memory (nvm) cell 有权
    一种用于制造逻辑晶体管和非易失性存储器（NVM）单元处理

    公开(公告)号：EP2725607A2

    公开(公告)日：2014-04-30

    申请号：EP13188538.6

    申请日：2013-10-14

    申请人： Freescale Semiconductor, Inc.

    发明人： Shroff, Mehul ,  Hall, Mark D

    IPC分类号： H01L21/8239 ,  H01L27/105

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/66545

    摘要： An oxide-containing layer (18) is formed directly on a semiconductor layer (12) in an NVM region (14), and a first partial layer (20) of a first material is formed over the oxide-containing layer in the NVM region. A first high-K dielectric layer (22) is formed directly on the semiconductor layer in a logic region (16). A first conductive layer (24) is formed over the first dielectric layer in the logic region. A second partial layer (26) of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer (28) if the cell is a floating gate cell or a select gate (28) if the cell is a split gate cell.

    Logic transistor and non-volatile memory cell integration
    7.
    发明公开
    Logic transistor and non-volatile memory cell integration 有权
    集成von Logiktransistor undnichtflüchtigenSpeicherzellen

    公开(公告)号：EP2650910A2

    公开(公告)日：2013-10-16

    申请号：EP13161836.5

    申请日：2013-03-29

    申请人： Freescale Semiconductor, Inc.

    发明人： Hall, Mark D. ,  Shroff, Mehul

    IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/04 ,  H01L21/28273 ,  H01L27/11534 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

    摘要： A first conductive layer (30) and an underlying charge storage layer (20) are patterned to form a control gate (32) in an NVM region (12). A first dielectric layer (34) and barrier layer (35) are formed over the control gate. A sacrificial layer (36) is formed over the barrier layer and planarized. A first patterned masking layer (38) in the NVM region defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer (38) defines a logic gate location in the logic region (14). Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location and a second portion remains at the logic gate location. A second dielectric layer (52) is formed over, and planarized to expose, the first and second portions. The first and second portions are removed to result in openings at the select gate location and at the logic gate location which expose the barrier layer.

    摘要翻译： 将第一导电层（30）和下面的电荷存储层（20）图案化以在NVM区域（12）中形成控制栅极（32）。 第一介电层（34）和阻挡层（35）形成在控制栅上。 牺牲层（36）形成在阻挡层上并且被平坦化。 NVM区域中的第一图案化掩模层（38）限定了与NVM区域中的控制栅极横向相邻的选择栅极位置。 第二掩蔽层（38）限定逻辑区域（14）中的逻辑门位置。 去除牺牲层的暴露部分，使得第一部分保持在选择栅极位置处，并且第二部分保持在逻辑门位置。 第二介电层（52）形成在第一和第二部分之上并且被平坦化以暴露第一和第二部分。 去除第一和第二部分以在选择栅极位置和暴露阻挡层的逻辑门位置处产生开口。

    METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE WITH ANTI-REFLECTIVE COATING
    8.
    发明授权
    METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE WITH ANTI-REFLECTIVE COATING 有权
    半导体存储元件的带防反射涂层的方法

    公开(公告)号：EP1222690B1

    公开(公告)日：2008-01-23

    申请号：EP00967129.8

    申请日：2000-09-29

    申请人： Spansion LLC

    发明人： HSAIO, Tommy, C. ,  RAMSBEY, Mark, T. ,  SUN, Yu

    IPC分类号： H01L21/8247 ,  H01L27/105

    CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/951

    摘要： Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by reducing ARC loss during photoresist stripping associated with plural mask formation in the core memory cell region during patterning and ion implantations. Embodiments include sequentially etching the stacked gate electrode structure in the core memory cell region, photoresist stripping and etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, plural maskings and ion implantations are implemented in the core memory cell region with attendant photoresist strippings.

    Electrically erasable and programable non-volatile memory cell
    9.
    发明公开
    Electrically erasable and programable non-volatile memory cell 审中-公开
    Elektrischlösch-und programmierbare nichtflüchtigeSpeicherzelle

    公开(公告)号：EP1376698A1

    公开(公告)日：2004-01-02

    申请号：EP02425416.1

    申请日：2002-06-25

    申请人： STMicroelectronics S.r.l.

    发明人： Cappelletti, Paolo ,  Ghezzi, Paolo ,  Maurelli, Alfonso ,  Vendrame, Loris ,  Zabberoni, Paola

    IPC分类号： H01L27/115 ,  G11C16/04

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

    摘要： An electrically erasable and programmable non-volatile memory cell (205) integrated in a chip of semiconductor material (300) is proposed. The memory cell includes a floating gate MOS transistor (210m) having a source region (335) and a drain region (325) formed in a first well (315), a channel (340) being defined between the drain region and the source region during operation of the memory cell, a control gate region (350), and a floating gate (355) extending over the channel and the control gate region, and a bipolar transistor (215) for injecting an electric charge into the floating gate, the bipolar transistor having an emitter region (365) formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel, wherein the memory cell further includes a second well (320) insulated from the first well, the control gate region being formed in the second well.

    摘要翻译： 提出了集成在半导体材料（300）的芯片中的电可擦除和可编程的非易失性存储单元（205）。 存储单元包括具有形成在第一阱（315）中的源极区（335）和漏极区（325）的浮置栅极MOS晶体管（210m），在漏极区域和源极区域之间限定沟道（340） 在所述存储单元的操作期间，在所述通道和所述控制栅极区域上延伸的控制栅极区域（350）和浮置栅极（355）以及用于将电荷注入所述浮动栅极的双极晶体管（215） 双极晶体管，其具有形成在第一阱中的发射极区域（365），由第一阱构成的基极区域和由沟道组成的集电极区域，其中存储单元还包括与第一阱绝缘的第二阱（320） ，所述控制栅极区域形成在所述第二阱中。

    Non-volatile semiconductor memory device having thin film memory transistors stacked over associated selecting transistors
    10.
    发明公开
    Non-volatile semiconductor memory device having thin film memory transistors stacked over associated selecting transistors 失效
    具有相关联的上层叠薄膜的存储器晶体管的相应选择晶体管的非易失性半导体存储装置。

    公开(公告)号：EP0544204A1

    公开(公告)日：1993-06-02

    申请号：EP92119897.4

    申请日：1992-11-23

    申请人： NEC CORPORATION

    发明人： Koyama, Shoji, c/o NEC Corporation ,  Inoue, Tatsuro, c/o NEC Corporation

    IPC分类号： H01L27/115 ,  G11C16/04

    CPC分类号： H01L27/11551 ,  G11C16/0483 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/7881

    摘要： A electrically erasable and programmable read only memory device has a memory cell array implemented by a plurality of floating gate type memory transistors, and each of the floating gate type memory transistors is implemented by a thin film field effect transistor with a floating gate electrode (16) formed over a relatively thick insulating film (13) covering a major surface of a semiconductor substrate (12) so that the biasing conditions and crystal defects do not have any influence on the floating gate type memory transistor.

    摘要翻译： 甲电可擦除和可编程只读存贮器件具有由浮置栅型存储晶体管的多元性实现的存储器单元阵列，并且每个浮置栅极型存储晶体管是由具有浮置栅电极的薄膜场效应晶体管来实现（16 ）形成在相对厚的绝缘电影（13），其覆盖一个半导体衬底（12）象偏置条件和晶体缺陷不会对浮置栅极型存储晶体管的任何影响的一个主表面上。