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    A METHOD FOR HIERARCHICAL SPECIFICATION OF SCHEDULING IN SYSTEM-LEVEL SIMULATIONS
    4.
    发明授权
    A METHOD FOR HIERARCHICAL SPECIFICATION OF SCHEDULING IN SYSTEM-LEVEL SIMULATIONS 有权
    法的时序仿真对系统级等级规格

    公开(公告)号：EP1327189B1

    公开(公告)日：2012-07-25

    申请号：EP01981725.3

    申请日：2001-10-17

    申请人： Cadence Design Systems, Inc.

    发明人： HOOVER, Christopher

    IPC分类号： G06F7/62 ,  G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/5045

    摘要： A method for hierarchical specification and modeling of scheduling in systemlevel simulations. A static scheduler is synthesized by a Virtual Component Codesign (VCC) process and comprises a simple sequential execution of the run functions (1-3) of behavious A-F. The invention addresses the specification aspect by introducing an explicit notion of a scheduler that must be designed as part of the system. A scheduler effectively represents a scheduling policy for an architectural resource. Two orthogal models, one of a scheduler and one of a schedulable, comprise the overall modeling of scheduling in the invention. The two models interact by sending messages to each other via a simple protocol. The protocol itself is implemented by a pair of abstract interfaces, which in turn are implemented in concrete schedulable and scheduler objects in the simulator.

    Method and apparatus for determining interactive electromagnetic effects among conductors of a multi-layer circuit
    5.
    发明公开
    Method and apparatus for determining interactive electromagnetic effects among conductors of a multi-layer circuit 审中-公开
    用于在多层电路的导体确定的交互式电磁效应的方法和装置

    公开(公告)号：EP1521188A3

    公开(公告)日：2010-09-29

    申请号：EP04256124.1

    申请日：2004-10-04

    申请人： Cadence Design Systems, Inc.

    发明人： Ling, Feng ,  Dengi, Enis Aykut ,  Okhmatovski, Vlamidir I.

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5018 ,  G06F17/5036 ,  G06F2217/78

    摘要： To estimate a distribution of voltages or currents in the layers of a multi-layer circuit, an exemplary current flow in each layer is discretized into a number of current vector elements and at least one scalar charge element related to the charge associated with each current vector element. A first distribution of voltages induced in each circuit layer is determined from current vector elements in all of the circuit layers. A second distribution of voltages induced in each circuit layer is determined from the scalar charge elements in all of the circuit layers. For each circuit layer, the first and second distributions of voltages induced therein are combined to determine an actual distribution of voltages in the circuit layer.

    Method and system for performing software verification
    7.
    发明公开
    Method and system for performing software verification 审中-公开
    方法和系统软件审核

    公开(公告)号：EP2204738A3

    公开(公告)日：2010-07-28

    申请号：EP09015071.5

    申请日：2009-12-04

    申请人： Cadence Design Systems, Inc.

    发明人： Andrews, Jason, Robert

    IPC分类号： G06F11/36 ,  G06F17/50

    CPC分类号： G06F11/3688 ,  G06F17/5022

    摘要： Described is a method, system, and computer program product that provides control of a hardware/software system, and allows deterministic execution of the software under examination. According to one approach, a virtual machine for testing software is used with a lightly synchronized stimulus for the software being tested. A verification tool external to the virtual machine is used to provide test stimulus to and to collect test information from the virtual machine. Test stimulus from the verification tool that is external to the virtual machine provides the stimulation that incrementally operates and changes the state of the virtual machine The stimulus is created and coverage is collected from outside the virtual machine by first stopping the virtual machine, depositing stimulus, and then reading coverage directly from the virtual machine memory while the machine is stopped.

    Method and system for performing software verification
    8.
    发明公开
    Method and system for performing software verification 审中-公开
    Verfahren und System zurSoftwareüberprüfung

    公开(公告)号：EP2204738A2

    公开(公告)日：2010-07-07

    申请号：EP09015071.5

    申请日：2009-12-04

    申请人： Cadence Design Systems, Inc.

    发明人： Andrews, Jason, Robert

    IPC分类号： G06F11/36

    CPC分类号： G06F11/3688 ,  G06F17/5022

    摘要： Described is a method, system, and computer program product that provides control of a hardware/software system, and allows deterministic execution of the software under examination. According to one approach, a virtual machine for testing software is used with a lightly synchronized stimulus for the software being tested. A verification tool external to the virtual machine is used to provide test stimulus to and to collect test information from the virtual machine. Test stimulus from the verification tool that is external to the virtual machine provides the stimulation that incrementally operates and changes the state of the virtual machine The stimulus is created and coverage is collected from outside the virtual machine by first stopping the virtual machine, depositing stimulus, and then reading coverage directly from the virtual machine memory while the machine is stopped.

    摘要翻译： 描述了一种提供对硬件/软件系统的控制的方法，系统和计算机程序产品，并允许确定性地执行被检查的软件。 根据一种方法，使用用于测试软件的虚拟机，对所测试的软件使用轻微同步的刺激。 虚拟机外部的验证工具用于向虚拟机提供测试刺激并从虚拟机收集测试信息。 来自虚拟机外部的验证工具的测试刺激提供增量操作和改变虚拟机状态的刺激。创建刺激，并通过首先停止虚拟机，存储刺激， 然后在机器停止时直接从虚拟机内存中读取覆盖。

    GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD
    9.
    发明公开
    GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD 审中-公开
    具有广义不利条件下收集程序

    公开(公告)号：EP2080129A2

    公开(公告)日：2009-07-22

    申请号：EP07843014.7

    申请日：2007-09-21

    申请人： Cadence Design Systems, Inc. ,  Arsintescu, George B.

    发明人： ARSINTESCU, George B.

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal. The specific constraints in a template type can be modified as technology changes, and the modification will automatically be applied to the design objects.