公开(公告)号：EP2681416A1

公开(公告)日：2014-01-08

申请号：EP12755169.5

申请日：2012-02-16

申请人： Karabatsos, Chris

发明人： Karabatsos, Chris

IPC分类号： F01B9/02

CPC分类号： F02B75/32

摘要： An engine comprises one or more cylinders, each cylinder comprising a piston, a connecting rod, a crank shaft, and a crankpin, wherein the crankpin further comprises a main crankpin and a crankpin extension, wherein the connecting rod is affixed at one end to the piston and at another end to a first end of the crankpin extension, wherein a second end of the crankpin extension is affixed to a first end of the main crankpin, and wherein a second end of the main crankpin is affixed to the crankshaft.

公开(公告)号：EP2681416A4

公开(公告)日：2015-04-15

申请号：EP12755169

申请日：2012-02-16

申请人： KARABATSOS CHRIS

发明人： KARABATSOS CHRIS

IPC分类号： F01B9/02

CPC分类号： F02B75/32

公开(公告)号：EP1290561A4

公开(公告)日：2006-10-11

申请号：EP01937381

申请日：2001-05-15

申请人： KARABATSOS CHRIS

发明人： KARABATSOS CHRIS

IPC分类号： G06F12/00 ,  G06F13/42 ,  G11C7/10

CPC分类号： G06F13/4243 ,  G11C7/10 ,  G11C7/1042

摘要： A computer memory system provides a double data rate (DDR) memory output while requiring memory chips with only half the frequency limit of the prior art DDR memory chips. The system contains a first bank memory bank 101 having data lines 106, and a second memory bank 102 having data lines 107. A basic system clock generates a delayed clock by means of a phase locked loop 140, or other phase shift device. The data lines of the first memory bank are connected with the data bus 116 in synchronism with the clock signal 104, while the data lines of the second memory bank are connected with the data bus 114 in synchronism with the delayed clock signal 105. As a result, the data bus is never connected to the data lines of both memory banks at the same time, but rather, the data bus is alternately connected with the first data bank and then the second data bank.

摘要翻译： 计算机存储器系统提供双倍数据速率（DDR）存储器输出，同时要求存储器芯片仅具有现有技术DDR存储器芯片的一半频率限制。 该系统包含具有数据线106的第一存储体存储体101和具有数据线107的第二存储体102.基本系统时钟借助于锁相环140或其他相移装置产生延迟时钟。 第一存储体的数据线与时钟信号104同步地与数据总线116连接，而第二存储体的数据线与延迟时钟信号105同步地与数据总线114连接。作为 结果，数据总线不会同时连接到两个存储体的数据线，而是数据总线交替地与第一数据库和第二数据库连接。

公开(公告)号：EP1092337A4

公开(公告)日：2004-07-21

申请号：EP99930417

申请日：1999-06-22

申请人： KARABATSOS CHRIS

发明人： KARABATSOS CHRIS

IPC分类号： H05K1/14 ,  H05K1/00 ,  G11C5/00

CPC分类号： H05K1/029 ,  H05K1/14 ,  H05K2201/10159 ,  H05K2201/10212 ,  H05K2201/10689

摘要： A method and apparatus for enhancing memory speed and capacity utilizes a set of electronic switches (24) to isolate the computer data bus (2) from the memory chips (16, 32, 34, 36). The apparatus includes one or more multi-sides memory boards (10, 12, 14) with etched leads (30, 42), lands and feed-through. The memory chips may be mounted on either one side or both sides of each board. Connection between the memory board and the motherboard is made by means of a comb of contact fingers (5) or edge-connector which mates with a connector (8) on the motherboard (28). The data lines and address lines of the computer bus are distinct from each other, and routed to the memory board via the edge connector (8). A set of CMOS TTL or FET switches (24) is located adjacent to the comb (5), and are switched on and off by a decoded combination of address, control, or data lines or by a distinct enable line provided by the CPU (3), controller or other decoding means located on the motherboard (28). As a result, only the memory chips actually required for the memory access are switched on, so that the other memory chips are isolated from the data bus (2). Because of this isolation, the capacitance of the non-switched components is not seen by the data bus, resulting in a lower overall capacitance, and a higher inherent memory access.

公开(公告)号：EP1290561A1

公开(公告)日：2003-03-12

申请号：EP01937381.0

申请日：2001-05-15

申请人： Karabatsos, Chris

发明人： Karabatsos, Chris

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G11C7/10 ,  G11C7/1042

摘要： A computer memory system provides a double data rate (DDR) memory output while requiring memory chips with only half the frequency limit of the prior art DDR memory chips. The system contains a first bank memory bank 101 having data lines 106, and a second memory bank 102 having data lines 107. A basic system clock generates a delayed clock by means of a phase locked loop 140, or other phase shift device. The data lines of the first memory bank are connected with the data bus 116 in synchronism with the clock signal 104, while the data lines of the second memory bank are connected with the data bus 114 in synchronism with the delayed clock signal 105. As a result, the data bus is never connected to the data lines of both memory banks at the same time, but rather, the data bus is alternately connected with the first data bank and then the second data bank.

摘要翻译： 计算机存储器系统提供双倍数据速率（DDR）存储器输出，同时要求存储器芯片仅具有现有技术DDR存储器芯片的一半频率限制。 该系统包含具有数据线106的第一存储体存储体101和具有数据线107的第二存储体102.基本系统时钟借助于锁相环140或其他相移装置产生延迟时钟。 第一存储体的数据线与时钟信号104同步地与数据总线116连接，而第二存储体的数据线与延迟时钟信号105同步地与数据总线114连接。作为 结果，数据总线不会同时连接到两个存储体的数据线，而是数据总线交替地与第一数据库和第二数据库连接。

公开(公告)号：EP1092337A1

公开(公告)日：2001-04-18

申请号：EP99930417.3

申请日：1999-06-22

申请人： Karabatsos, Chris

发明人： Karabatsos, Chris

IPC分类号： H05K1/14

CPC分类号： H05K1/029 ,  H05K1/14 ,  H05K2201/10159 ,  H05K2201/10212 ,  H05K2201/10689

摘要： A method and apparatus for enhancing memory speed and capacity utilizes a set of electronic switches (24) to isolate the computer data bus (2) from the memory chips (16, 32, 34, 36). The apparatus includes one or more multi-sides memory boards (10, 12, 14) with etched leads (30, 42), lands and feed-through. The memory chips may be mounted on either one side or both sides of each board. Connection between the memory board and the motherboard is made by means of a comb of contact fingers (5) or edge-connector which mates with a connector (8) on the motherboard (28). The data lines and address lines of the computer bus are distinct from each other, and routed to the memory board via the edge connector (8). A set of CMOS TTL or FET switches (24) is located adjacent to the comb (5), and are switched on and off by a decoded combination of address, control, or data lines or by a distinct enable line provided by the CPU (3), controller or other decoding means located on the motherboard (28). As a result, only the memory chips actually required for the memory access are switched on, so that the other memory chips are isolated from the data bus (2). Because of this isolation, the capacitance of the non-switched components is not seen by the data bus, resulting in a lower overall capacitance, and a higher inherent memory access.