公开(公告)号：EP2973683B1

公开(公告)日：2018-10-24

申请号：EP14719954.1

申请日：2014-03-13

申请人： Nthdegree Technologies Worldwide Inc.

发明人： RAY, William Johnstone ,  BLANCHARD, Richard Austin ,  LOWENTHAL, Mark David ,  ORAW, Bradley Steven

IPC分类号： H01L21/98 ,  H01L25/065 ,  H01L25/075 ,  H01L33/20 ,  H01L21/60 ,  H05K1/02 ,  H05K3/12

CPC分类号： H01L24/95 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/18 ,  H01L25/50 ,  H01L33/20 ,  H01L2221/68381 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/25105 ,  H01L2224/25174 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82143 ,  H01L2224/92244 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95115 ,  H01L2224/95143 ,  H01L2224/95146 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H05K1/029 ,  H05K1/0296 ,  H05K3/12

摘要： A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

公开(公告)号：EP2479690B9

公开(公告)日：2018-03-28

申请号：EP12154766.5

申请日：2005-09-22

申请人： Digi International Inc. Delaware Corporation

发明人： Rogers, Norman L. ,  Hoffman, John W. ,  Feng, Jun ,  Krauter, Charles

IPC分类号： G06F17/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC分类号： G06F17/5068 ,  H05K1/0206 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/111 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/0064 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124

摘要： A method and apparatus for configurable circuitry have been disclosed.

公开(公告)号：EP1240668B1

公开(公告)日：2011-08-24

申请号：EP00973889.9

申请日：2000-10-25

申请人： Intel Corporation

发明人： HORIGAN, John, W. ,  MORESCO, Larry, L.

IPC分类号： H01L23/544 ,  H05K1/02

CPC分类号： H05K1/0266 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2924/01004 ,  H05K1/029 ,  H05K3/3436 ,  H05K2201/10734

摘要： An integrated circuit (IC) package includes a substrate, a ground line, and an encoded region. The encoded region provides information based upon selective deposition of solder balls electrically coupled to the ground line.

公开(公告)号：EP1063663B1

公开(公告)日：2007-08-15

申请号：EP00305322.0

申请日：2000-06-23

申请人： GENERAL ELECTRIC COMPANY

发明人： Criniti, Joseph ,  Wambolt, Lee Anne ,  Larranaga, Javier Ignacio ,  Messerli, Alan Joseph

IPC分类号： H01H3/00 ,  H02H3/00 ,  H05K13/04

CPC分类号： H02H3/006 ,  H05K1/029 ,  H05K2201/10022 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2203/0195 ,  H05K2203/176 ,  Y02P70/611 ,  Y10T29/53274

公开(公告)号：EP1483722B1

公开(公告)日：2007-04-18

申请号：EP03713706.4

申请日：2003-02-24

申请人： Celetronix International, Ltd ,  Celetronix USA, Inc.

发明人： PEDDLE, Charles, I.

IPC分类号： G11C29/00 ,  G11C5/06

CPC分类号： H01L22/20 ,  B82Y10/00 ,  G11C5/063 ,  G11C29/022 ,  G11C29/88 ,  G11C29/886 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/4899 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/162 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of fabricating a memory module according to one embodiment, a clock booster is mounted on a multi-layer circuit bard (101). The clock booster may be any apparatus that receives a clock input, and output one or more clock signals capable of driving a multiplicity of logic parts without clock distortion. In a preferred embodiment, a phase-locked loop circuit may be used as a clock booster. The test and patching (102) allows a fully-functional memory part adds, it is desirable to only connect the clock signal to those memory parts that are utilized. This may be accomplished using any number of switching mechanisms to connect or disconnect a clock signal to a memory part. In a preferred embodiment, a clock patching network may be used to selectively connect or disconnect outputs of a clock booster to the memory parts (103).

公开(公告)号：EP1582093A2

公开(公告)日：2005-10-05

申请号：EP03725998.3

申请日：2003-02-24

申请人： Celetronix International, Ltd ,  Celetronix USA, Inc.

发明人： PEDDLE, Charles, I.

IPC分类号： H05K1/00

CPC分类号： B82Y10/00 ,  G11C29/02 ,  G11C29/022 ,  G11C29/88 ,  G11C29/886 ,  H01L22/20 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/4899 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/029 ,  H05K1/181 ,  H05K3/225 ,  H05K2201/10159 ,  H05K2203/162 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method and apparatus for building a memory module using improved patching schemes comprises, mounting multiple primary and secondary memory parts on a mufti-layer circuit board (111), positioning I/O bit line patching networks adjacent to the primary and secondary memory parts (112), matching read/write control signals for primary and secondary memory parts which share I/O bit line patching networks (113), testing primary and secondary memory parts to identify non-operable I/O lines (114), and patching any non-operable I/O line of a primary memory part by replacing it with a fully operable I/O line of its associated backup memory part (115). The method and apparatus include mufti-layer circuit boards which utilize 2-to 1, 4-to-1, and 8-to-1 patching configurations.

公开(公告)号：EP1483722A1

公开(公告)日：2004-12-08

申请号：EP03713706.4

申请日：2003-02-24

申请人： Celetronix International, Ltd ,  Celetronix USA, Inc.

发明人： PEDDLE, Charles, I.

IPC分类号： G06F19/00

CPC分类号： H01L22/20 ,  B82Y10/00 ,  G11C5/063 ,  G11C29/022 ,  G11C29/88 ,  G11C29/886 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/4899 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/162 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of fabricating a memory module according to one embodiment, a clock booster is mounted on a multi-layer circuit bard (101). The clock booster may be any apparatus that receives a clock input, and output one or more clock signals capable of driving a multiplicity of logic parts without clock distortion. In a preferred embodiment, a phase-locked loop circuit may be used as a clock booster. The test and patching (102) allows a fully-functional memory part adds, it is desirable to only connect the clock signal to those memory parts that are utilized. This may be accomplished using any number of switching mechanisms to connect or disconnect a clock signal to a memory part. In a preferred embodiment, a clock patching network may be used to selectively connect or disconnect outputs of a clock booster to the memory parts (103).

公开(公告)号：EP1092337A4

公开(公告)日：2004-07-21

申请号：EP99930417

申请日：1999-06-22

申请人： KARABATSOS CHRIS

发明人： KARABATSOS CHRIS

IPC分类号： H05K1/14 ,  H05K1/00 ,  G11C5/00

CPC分类号： H05K1/029 ,  H05K1/14 ,  H05K2201/10159 ,  H05K2201/10212 ,  H05K2201/10689

摘要： A method and apparatus for enhancing memory speed and capacity utilizes a set of electronic switches (24) to isolate the computer data bus (2) from the memory chips (16, 32, 34, 36). The apparatus includes one or more multi-sides memory boards (10, 12, 14) with etched leads (30, 42), lands and feed-through. The memory chips may be mounted on either one side or both sides of each board. Connection between the memory board and the motherboard is made by means of a comb of contact fingers (5) or edge-connector which mates with a connector (8) on the motherboard (28). The data lines and address lines of the computer bus are distinct from each other, and routed to the memory board via the edge connector (8). A set of CMOS TTL or FET switches (24) is located adjacent to the comb (5), and are switched on and off by a decoded combination of address, control, or data lines or by a distinct enable line provided by the CPU (3), controller or other decoding means located on the motherboard (28). As a result, only the memory chips actually required for the memory access are switched on, so that the other memory chips are isolated from the data bus (2). Because of this isolation, the capacitance of the non-switched components is not seen by the data bus, resulting in a lower overall capacitance, and a higher inherent memory access.

公开(公告)号：EP0998176B1

公开(公告)日：2003-12-10

申请号：EP99116665.3

申请日：1999-08-26

申请人： ROBERT BOSCH GMBH

发明人： Lamm, Hubert ,  Steuer, Peter ,  Haderer, Guenter

IPC分类号： H05K5/00 ,  G05B19/042 ,  G11C16/10

CPC分类号： H05K5/0026 ,  G05B2219/13168 ,  H05K1/029 ,  H05K1/0293 ,  H05K2201/0191 ,  H05K2201/0999 ,  H05K2203/1115 ,  H05K2203/1189 ,  H05K2203/175

公开(公告)号：EP1339269A1

公开(公告)日：2003-08-27

申请号：EP03002198.4

申请日：2003-02-04

申请人： Harting Automotive GmbH & Co. KG

发明人： Krause, Jens, Dr.-Ing.

IPC分类号： H05K3/22

CPC分类号： H05K3/225 ,  H05K1/0266 ,  H05K1/029 ,  H05K1/0293 ,  H05K2201/09063 ,  H05K2203/0195 ,  H05K2203/0228 ,  H05K2203/175

摘要： Die Erfindung betrifft ein Kodierelement (16) für ein elektrisches Modul (30), mit mindestens einer Schneide (18), die dafür vorgesehen ist, eine von mehreren auf einem Substrat (10) angeordneten Leiterbahnen (12) zu durchtrennen, wodurch dem elektrischen Modul (30) eine Adresse zugeordnet wird. Die Erfindung betrifft auch ein elektrisches Modul mit einem solchen Kodierelement.

摘要翻译： 该装置具有布置在基底由电绝缘材料制成的切削刃（18），所有这些被设置以切断导体轨道中的一个（12）分配到电动模块的地址。 切削刃设置有弯曲的偏转面。 定心销（22）被提供在基板接合在所述开口（14）。