公开(公告)号：EP2064524A1

公开(公告)日：2009-06-03

申请号：EP07716177.6

申请日：2007-03-28

申请人： PLETERSEK, Anton

发明人： VODOPIVEC, Andrej

IPC分类号： G01D5/244

CPC分类号： G01D5/2448 ,  G01D5/24452 ,  G01D5/2449

摘要： Input signals having the same functional time dependence, e.g. a sinusoidal one, and being out-of-phase with regard to each other are amplified selectively according to the result of a previous comparison of the amplitudes of a first and a second matched signals (s1m, s2m), which were formed from the input signals (s1, s2) by means of said selective amplifying, which step-by-step matches the output signals to each other in amplitude. There is measured the duration (T) of a time interval between such passings of the matched signals through a signal ground (gnd) that both matched signals have the same polarity in said time interval. It is ascertained on the basis of the time duration (T) that the frequency of the input signals is within preset frequency limits. The first matched signal is sampled the moment the second matched signal passed through the signal ground and the second one the moment the first one passed through the signal ground. Values obtained by sampling are compared to each other. A selective gain control signal is generated as a result of said comparison of the sample values. The gain applied to either input signal is increased or decreased. The method of the invention for automatically controlling the amplitude of input signals initiates an automatic selective amplification of individual input signals.

公开(公告)号：EP2079988B1

公开(公告)日：2010-07-07

申请号：EP07716178.4

申请日：2007-03-28

申请人： PLETERSEK, Anton

发明人： BENKOVIC, Roman

IPC分类号： G01D5/244

CPC分类号： G01D5/24404 ,  G01D5/24409

公开(公告)号：EP2079988A1

公开(公告)日：2009-07-22

申请号：EP07716178.4

申请日：2007-03-28

申请人： PLETERSEK, Anton

发明人： BENKOVIC, Roman

IPC分类号： G01D5/244

CPC分类号： G01D5/24404 ,  G01D5/24409

摘要： Intermediate digital signals Fi(α), Gi(α), i = 1,...I are generated, which result from a comparison of reference potentials of the first input analogue signal at a shifted value of its observed argument and with a suitably reduced amplitude to the potential, which is inverse to said potential, of the third input analogue signal at the same shifted value of the observed argument and with the amplitude reduced in said way, the shifted argument values being uniformly distributed within the first half-period. A value U of the voltage is measured at any value of the observed argument as at that time the highest one of the voltages at terminals with said reference potentials. An actual peak amplitude A of the input analogue signals is determined as A = kI,m1U where the factor kI,mU is a quotient of the peak amplitude of said input analogue signals and of the mean value of the voltage waveform envelope of the reference potentials pertaining to said peak amplitude. When the proposed method is used to automatically control the gain, said voltage U is conducted directly to the input of an automatic gain control circuit, whereat the input voltage of this circuit is set to the mean value of the voltage waveform envelope of the reference potentials.

公开(公告)号：EP1642183A1

公开(公告)日：2006-04-05

申请号：EP03817450.4

申请日：2003-07-09

申请人： PLETERSEK, Anton

发明人： PLETERSEK, Anton

IPC分类号： G05F3/24 ,  G05F3/26

CPC分类号： G05F3/267 ,  G05F3/245 ,  G05F3/262 ,  Y10S323/907

摘要： A circuit of the invention comprises a low voltage PTAT source. Current generators (t1, t2) are controlled so that their output currents I1 and I2, respectively, have temperature properties of the quotient VPTAT/R. The current I1 is conducted to a first terminal (X) on a first connection of a composition of series connected resistors (Ra, Rb), a second connection thereof being grounded. A transistor (T) is diodelike forward connected between the first terminal (X) and the ground. The current I2 is conducted to a second terminal (Y), preferably being at the same time a common connection (Z) of the resistors (Ra, Rb). Reference voltage Vr is tapped from the connection (Z). Said resistors (Ra, Rb) are manufactured in the n-well technology in the same way as the resistor (R), with the resistance of which the mentioned quotient is generated. The proposed circuit is distinguished for its current controlled summing regulator, which is also suggested by the invention, and which makes it possible that in a temperature range from -50 °C to 150 °C a very low reference voltage of 0.35 V at low supply voltage lying below 0.9 V is reached, and does not simultaneously introduce nonideal behaviour like offset voltage.