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    Distributed procedure execution and file systems on a memory interface
    1.
    发明公开
    Distributed procedure execution and file systems on a memory interface 有权
    VerteiltProzedurausführungund Dateisysteme an einer Speicherschnittstelle

    公开(公告)号：EP2911065A1

    公开(公告)日：2015-08-26

    申请号：EP15156155.2

    申请日：2015-02-23

    申请人： Rambus Inc. ,  Perego, Richard ,  Rambus Inc.

    发明人： Woo, Steven ,  Perego,, Richard ,  Batra, Pradeep ,  Lai, Lawrence ,  Yeung, Chi-Ming

    IPC分类号： G06F13/16 ,  G06F12/06

    CPC分类号： G06F13/1694 ,  G06F12/0638

    摘要： Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a DRAM memory channel. Nonvolatile memory residing on a DRAM memory channel may be integrated into the existing file system structures of operating systems. The nonvolatile memory residing on a DRAM memory channel may be presented as part or all of a distributed file system. Requests and/or remote procedure call (RPC) requests, or information associated with requests and/or RPCs, may be routed to the memory modules over the DRAM memory channel in order to service compute and/or distributed file system commands.

    摘要翻译： 非易失性存储器（例如，闪存，固态盘）被包括在DRAM存储器通道上的存储器模块上。 驻留在DRAM存储器通道上的非易失性存储器可以被集成到操作系统的现有文件系统结构中。 驻留在DRAM存储器通道上的非易失性存储器可以被呈现为分布式文件系统的一部分或全部。 可以通过DRAM存储器通道将请求和/或远程过程调用（RPC）请求或与请求和/或RPC相关联的信息路由到存储器模块，以便为计算和/或分发的文件系统命令提供服务。

    MEMORY SYSTEM WITH POINT-TO POINT REQUEST INTERCONNECT
    2.
    发明公开
    MEMORY SYSTEM WITH POINT-TO POINT REQUEST INTERCONNECT 审中-公开

    公开(公告)号：EP4451270A2

    公开(公告)日：2024-10-23

    申请号：EP24193358.9

    申请日：2008-04-11

    申请人： Rambus Inc.

    发明人： PEREGO, Richard, E. ,  WARE, Frederick, A.

    IPC分类号： G11C7/10

    摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

    MULTI-DIE MEMORY DEVICE
    4.
    发明公开
    MULTI-DIE MEMORY DEVICE 审中-公开

    公开(公告)号：EP4254413A2

    公开(公告)日：2023-10-04

    申请号：EP23187607.9

    申请日：2007-12-13

    申请人： Rambus Inc.

    发明人： BEST, Scott ,  LI, Ming

    IPC分类号： G11C5/02

    摘要： An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission.

    BURST-TOLERANT DECISION FEEDBACK EQUALIZATION
    5.
    发明公开
    BURST-TOLERANT DECISION FEEDBACK EQUALIZATION 审中-公开

    公开(公告)号：EP3883129A1

    公开(公告)日：2021-09-22

    申请号：EP21155399.5

    申请日：2016-07-22

    申请人： Rambus Inc.

    发明人： GIOVANNI, Thomas, J. ,  ABHYANKAR, Abhijit

    IPC分类号： H03H7/30 ,  G06F3/06 ,  G11C19/00 ,  H04L25/03

    摘要： A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.